Low voltages in two stress modes and at three temperatures were applied to two kinds of p-channel metal-oxidesemiconductor field-effect transistors (pMOSFETs) to investigate the substrate current variations and hot-carrier (HC)induced degradation. Contrary to conventional concepts, this investigation reveals that the worst conditions for pMOSFET HC reliability involve channel HC (CHC) mode and high temperatures. The severity of degradation of pMOSFETs has become comparable to their n-channel MOSFET (nMOSFET) counterparts. A probable damage mechanism is suggested to involve the generation of interface states owing to the integration of HCs and the negative-biased temperature effect (NBTI). A new empirical lifetime model is proposed in terms of applied voltages and temperatures.

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In this study, n-channel metal–oxide–semiconductor field-effect transistors (nMOSFETs) having 20 and 32 Å gate oxide thicknesses of 0.13 µm technology were used to investigate DC hot-carrier reliability at elevated temperatures up to 125 °C. The research also focused on the degradation of analog properties after hot-carrier injection. On the basis of the results of experiments, the hot-carrier degradation of Id,op (drain current defined on the basis of analog applications) is found to be the worst case among those of three types of drain current from room temperature to 125 °C. This result should provide valuable insight to analog circuit designers. As to the reverse temperature effect, the substrate current (Ib) commonly accepted as the parameter for monitoring the drain-avalanche-hot-carrier (DAHC) effect should be modified since the drain current (Id) degradation and Ib variations versus temperature have different trends. For the devices having a gate oxide thinner than 20 Å, we suggest that the worst condition in considering hot-carrier reliability should be placed at elevated temperatures.

In this paper, the impact of hot carrier stress on the mismatch properties of n and p metal–oxide–semiconductor (MOS) field-effect transistors (FETs) with different sizes produced using 0.15 µm complementary MOS (CMOS) technology is presented for the first time. The research reveals that hot-carrier injection (HCI) does degrade the matching properties of MOSFETs. The degree of degradation closely depends on the strength of the HC effect. Thus, it is found that, under the stress condition of drain avalanche hot carrier (DAHC), the properties of nMOSFETs rapidly and greatly become worse, but the changes are small for pMOSFETs. For analog circuit parameters, it is found that the after-stress lines of n and pMOSFETs exhibit a cross point in σ (ΔVt,op) drawings. It is suggested that the cross point can be used to indicate the minimal size in order for n and p pairs to have the same degree of ΔVt,op mismatch in designing analog circuits. In addition, interpretations for the differences between n and pMOSFETs and between ΔVt,op and Ids,op mismatches are provided with experimental verifications.

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