Metal-oxide-semiconductor capacitors (MOSCs) and MOS field-effect transistors (MOSFETs) incorporating cerium dioxide (CeO 2 ) dielectrics were fabricated and investigated. In this work, the electrical and interfacial properties were characterized by capacitancevoltage (C-V ) and current-voltage (I-V ) measurements. The density of interface trap per unit area (N it ), the density of interface trap per unit area and energy (D it ), the energy distribution of interface trap density, and the effective capture cross section ( s ) were studied in details. Experimental results showed that the N it , D it , and s were about 3:4 Â 10 10 cm À2 , 7:3 Â 10 10 cm À2 eV À1 , and 9:0 Â 10 À15 cm 2 , respectively. In addition, a comparison of interfacial properties among several gate dielectrics was made.

No abstract

No abstract

Low voltages in two stress modes and at three temperatures were applied to two kinds of p-channel metal-oxidesemiconductor field-effect transistors (pMOSFETs) to investigate the substrate current variations and hot-carrier (HC)induced degradation. Contrary to conventional concepts, this investigation reveals that the worst conditions for pMOSFET HC reliability involve channel HC (CHC) mode and high temperatures. The severity of degradation of pMOSFETs has become comparable to their n-channel MOSFET (nMOSFET) counterparts. A probable damage mechanism is suggested to involve the generation of interface states owing to the integration of HCs and the negative-biased temperature effect (NBTI). A new empirical lifetime model is proposed in terms of applied voltages and temperatures.

In this study, n-channel metal–oxide–semiconductor field-effect transistors (nMOSFETs) having 20 and 32 Å gate oxide thicknesses of 0.13 µm technology were used to investigate DC hot-carrier reliability at elevated temperatures up to 125 °C. The research also focused on the degradation of analog properties after hot-carrier injection. On the basis of the results of experiments, the hot-carrier degradation of Id,op (drain current defined on the basis of analog applications) is found to be the worst case among those of three types of drain current from room temperature to 125 °C. This result should provide valuable insight to analog circuit designers. As to the reverse temperature effect, the substrate current (Ib) commonly accepted as the parameter for monitoring the drain-avalanche-hot-carrier (DAHC) effect should be modified since the drain current (Id) degradation and Ib variations versus temperature have different trends. For the devices having a gate oxide thinner than 20 Å, we suggest that the worst condition in considering hot-carrier reliability should be placed at elevated temperatures.