The switch of the worst case on NBTI and hot-carrier reliability for 0.13μm pMOSFETs

Transistor variability after CHC and NBTI stress in 90 nm pMOSFET technology

“…However, subsequent reports revealed that the worse condition of HC effects on pMOSFETs had switched from low temperature to high temperature and from DAHC to channel hot carrier (CHC) mode [7]. Also, the NBTI effects appear even worse than CHC mode at high temperature [8]. Hence, it is important to compare the severity of mismatches for pMOSFETs subjected to both CHC and NBTI stress.…”

Effects of Negative Bias Temperature Stress-induced Degradation and Mismatch on pMOSFETs in 90 nm Technology

“…It is speculated that nitrogen incorporation into gate dielectric made NBTI worse although it increases dielectric constant and reduces boron penetration. Then, using the lifetime model provided from [10], Fig. 6 shows the predicted lifetimes of pMOSFETs with different T ox after NBTI.…”

“…Further, there were other reports revealed that worse condition of HC effects on pMOSFETs have occurred in CHC at high temperature [4]. NBTI appears even worse than CHC at high temperature [10]. So, the severity of pMOSFET mismatches subjected to both CHC and NBTI stress should be understood.…”

Using Power Transform to Study DC and AC CHC Effects on nMOSFETs in 65 nm Technology

“…As the shrinking of the device size, channel hot-carrier (CHC) is the most critical reliability issue on MOSFETs in CMOS technology [1][2][3]. It is well-known that DC HC reliability test is usually executed with constant voltage stress (CVS) to investigate MOSFET degradation and to evaluate device lifetime (τ) in wafer foundry.…”