No abstract

FinFET technology is used in leading highperformance/power-efficient electronic products. This technology has proven its efficiency after 22nm technology nodes. However, FinFET technology has new manufacturing and design complexities. Thus, it is required to study the behavior of defects in FunFET-based SRAM memories, and developing new test strategies for those defects that are not covered by conventional test strategies based on CMOS fault modeling. This paper is oriented to open-gate defects hard-to-detect that are unique to FinFET based SRAM memory cells. The open-gate defect affects only one of the parallel fins of the driver transistors of the memory cell. The behavior of these defects is studied for the hold, read and write operations using realistic defect models. By using a shorter write time test, the detection of these defects is investigated. The effectiveness of the shorter write time test method at nominal parameters and under process variations is evaluated. The detection probability of these defects can be further enhanced using a higher power supply voltage.