We address access control of reconfigurable scan networks, like IEEE Std. 1687 networks. We propose an onchip test block to perform: (1) test for faulty scan-chains, (2) localization of faulty scan-chains and (3) repair by excluding faulty scan-chains, and an access control block to (1) control so scanchains (instruments) are only accessed in allowed combinations, (2) detection of access attempts to instrument in not allowed combinations, and (3) monitoring how theses attempts are made. The key features are twofold. First, in respect to operation and maintenance. If the physical implementation of an IEEE Std. 1687 network changes due to faults, the instrument connectivity language (ICL) and procedural description language (PDL) need to be updated. To avoid keeping track and updating ICL and PDL for each individual integrated circuit (IC), proposed test block, placed at each IC, makes adjustments of PDL according to the faults of the particular IC. Second, a centralized access control block with key information about the network to detect and handle unauthorized access.

Modern integrated circuits (ICs) include thousands of on-chip instruments to ensure that specifications are met and maintained. Scalable and flexible access to these instruments is offered by reconfigurable scan networks (RSNs), e.g., IEEE Std. 1687. As RSNs themselves can become faulty, there is a need to exclude and bypass faulty parts so that remaining instruments can be used. To avoid keeping track and updating description languages for each individual IC, we propose an on-chip hardware block that makes adjustments according to the fault status of a particular IC. We show how this block enables test for faulty scan chains, localization of faulty scan chains, and repair by excluding faulty scan chains. We made implementations and experiments to evaluate the overhead in terms of transported data and area.