Transformers have an important role from the production of electricity energy to consumption. Because they are responsible for ensuring that power transfer is carried out appropriately in many stages. Therefore, power transformers work in many places, from the production phase of electricity to the transmission and distribution phases. If various time periods are taken into consideration for energy using, power transformers can operate at small powers or very small powers. This small-power operation, which can be defined even as minor quantity, is counterproductive as a proportional increase in energy loss. The small working power, because of this loss ratio, is not taken into consideration; but considering large number of power transformers in annual periods, it can cause the serious losses and the costs emerge. In this paper, we propose a dual transformer control model in which apparent time periods with little load are determined by software, and in those periods, the load is fed by power transformers of smaller power or fewer. In this model, we worked for reducing the amount of power loss and energy costs during periods. Reduced load is demonstrated in following parts by statistical results.

Purpose This paper aims to present a single-block memory-based FFT processor design with a conflict-free addressing scheme for field-programmable gate arrays FPGAs with dual-port block memories. This study aims for a single-block dual-port memory-based N-point radix-2 FFT design that uses memory locations and spending minimum clock cycle. Design/methodology/approach A new memory-based Fast Fourier Transform (FFT) design that uses a dual-port memory block is proposed. Dual-port memory allows the design to perform two memory reads and writes in a single clock cycle. This approach achieves low operational clock and smallest memory simultaneously, excluding some small overhead for exceptional address changes. The methodology is to read from while writing to a memory location, eliminating the need for excess memory and additional clock cycles. Findings With the minimum memory size and the simplest architecture, radix-2 FFT and single-memory block are used. The number of clock pulses spent for all FFT operations does not provide much advantage for low-point FFT operations but is important for high-point FFT operations. With the developed algorithm, N memory is used, and the number of clock pulses spent for all FFT stages is (N/2 +1)log2N for all FFT operations. Originality/value This is an original paper, which has simultaneously in whole or in part been submitted anywhere else.

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A new efficient memory-based FFT calculation method is presented using dual-port memories. Algorithm mainly targets Field Programmable Gate Arrays (FPGA). A semi-in-place calculation of FFT stages is presented to have both reads and writes in a single clock while keeping the memory size equal to the FFT size. The "semi-" word implies that the writes are not to the original/expected position. At each intermediate calculation, the outputs are written to the position where the reads are done so that the unused data is not overwritten. Compared to multi-bank memory FFT approaches, proposed memory addressing schema is both simpler to logically establish and requires lower count of logical elements. It is shown that the proposed approach accomplishes FFT task in lowest count of clock cycles among the single bank memory-based FFT algorithms. However, two-port single-bank size-N memory requirement limits the proposed design to radix-2.

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