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The time it takes to acquire a satellite signal is one of the most important parameters for a Global Navigation Satellite System (GNSS) receiver. The Parallel Frequency space search acquisition Algorithm (PFA) runs faster than the Parallel Code phase search acquisition Algorithm (PCA) when the approximate phase of Pseudo-Random Noise (PRN) code and the approximate value of a Doppler shift are known. However, a large amount of data is needed to be dealt with by the Fast Fourier Transform (FFT) in a traditional PFA algorithm because it processes a narrow-band signal with the initial sampling frequency after the PRN code is stripped. In order to reduce the computational complexity of the traditional PFA algorithm, a down-conversion module and a downsampling module were added to the traditional PFA in the work reported here. Experiments demonstrated that this method not only succeeded in acquiring BeiDou B1I signals, but also the time for acquirement was reduced by at least 80% with the modified PFA algorithm compared with the traditional PFA algorithm. The loss in Signal-to-Noise Ratio (SNR) did not exceed 0·5 dB when the number of coherent points was less than 500.

An adaptive quaternion particle filter (QPF) based on the generalized likelihood ratio test (GLRT) is proposed for aircraft attitude estimation in the presence of an anomalous measurement. The framework of the QPF is employed to guarantee quaternion normalization. To cope with an anomalous measurement when interference occurs, the proposed algorithm uses the GLRT to detect an anomalous measurement and determine the interference source. An adaptation scheme is used to tune the measurement noise covariance matrix after the interference source has been determined so that the algorithm can remain robust against interference. Numerical simulations are carried out to evaluate the performance of the proposed algorithm and compare it with the QPF algorithm. The results show that the proposed algorithm outperforms the standard one in attitude estimation accuracy under anomalous measurement conditions.

Evolvable hardware (EHW) based on field-programmable gate arrays (FPGAs) opens up new possibilities towards building efficient adaptive system. State of the art EHW systems based on virtual reconfiguration and dynamic partial reconfiguration (DPR) both have their limitations. The former has a huge area overhead and circuit delay, and the later has slow configuration speed and low flexibility. Therefore a general low-cost fast hybrid reconfiguration architecture is proposed in this paper, which merges the high flexibility of virtual reconfiguration and the low resource cost of DPR. Moreover, the bitstream relocation technology is introduced to save the bitstream storage space, and the discrepancy configuration technology is adopted to reduce reconfiguration time. And an embedded RAM core is adopted to store bitstreams which accelerate the reconfiguration speed further. The proposed architecture is evaluated by the online evolution of digital image filter implemented on the Xilinx Virtex-6 FPGA development board ML605. And the experimental results show that our system has lower resource overhead, higher operating frequency, faster reconfiguration speed and less bitstream storage space in comparison with the previous works.

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