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Bias non-conservation characteristics of radio-frequency noise mechanism of 40-nm n-MOSFET are observed by modeling and measuring its drain current noise. A compact model for the drain current noise of 40-nm MOSFET is proposed through the noise analysis. This model fully describes three kinds of main physical sources that determine the noise mechanism of 40-nm MOSFET, i.e., intrinsic drain current noise, thermal noise induced by the gate parasitic resistance, and coupling thermal noise induced by substrate parasitic effect. The accuracy of the proposed model is verified by noise measurements, and the intrinsic drain current noise is proved to be the suppressed shot noise, and with the decrease of the gate voltage, the suppressed degree gradually decreases until it vanishes. The most important findings of the bias non-conservative nature of noise mechanism of 40-nm n-MOSFET are as follows. (i) In the strong inversion region, the suppressed shot noise is weakly affected by the thermal noise of gate parasitic resistance. Therefore, one can empirically model the channel excess noise as being like the suppressed shot noise. (ii) In the middle inversion region, it is almost full of shot noise. (iii) In the weak inversion region, the thermal noise is strongly frequency-dependent, which is almost controlled by the capacitive coupling of substrate parasitic resistance. Measurement results over a wide temperature range demonstrate that the thermal noise of 40-nm n-MOSFET exists in a region from the weak to strong inversion, contrary to the predictions of suppressed shot noise model only suitable for the strong inversion and middle inversion region. These new findings of the noise mechanism of 40-nm n-MOSFET are very beneficial for its applications in ultra low-voltage and low-power RF, such as novel device electronic structure optimization, integrated circuit design and process technology evaluation.

This study systematically investigates identical pulse stimulation for potentiation machine learning to achieve a linear potentiation non-linearity (α P ) equal to 1.25 and a high conductance ratio >1,000x with 5 nm-thick HfZrO 2 (HZO) ferroelectric field effect transistors (FeFET). The trade-off characteristics between conductance ratio and linearity are exhibited. The higher remnant polarization (P r ) for memory window (MW) enhancement leads to an increasing conductance ratio but degrades the non-linearity of the training curve. The optimized stimulation condition for the identical pulse is performed with a pulse width of 50 ns and low access voltage for HZO thicknesses from 15 to 5 nm. These highlighted merits provide an opportunity to integrate emerging devices such as computing-in-memory (CIM) applications in the future.