Based on a theoretical model of Q-switched laser with the influences of the driving signal sent to the Pockels cell and the doping concentration of the gain medium taken into account, a method of achieving high energy sub-nanosecond Q-switched lasers is proposed and verified in experiment. When a Nd:YVO4 crystal with a doping concentration of 0.7 at.% is used as a gain medium and a driving signal with the optimal high-level voltage is applied to the Pockels cell, a stable single-transverse-mode electro–optical Q-switched laser with a pulse width of 0.77 ns and a pulse energy of 1.04 mJ operating at the pulse repetition frequency of 1 kHz is achieved. The precise tuning of the pulse width is also demonstrated.

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A theoretical model suitable to the dual-wavelength electro-optical Q-switched laser was established. Based on the optimizations on the time-varying Q-switched loss, doped concentration of the gain medium, and transmission of the output coupler, 1 kHz 1064 nm and 532 nm single-longitudinal-mode pulse lasers both with sub-nanosecond pulse width (PW) were obtained. The measured PWs of the dual-wavelength lasers agreed well with the theoretical predictions. At a pump energy of 3.7 mJ, the PWs of the 1064 nm and 532 nm lasers were 0.97 ns and 0.61 ns, the single pulse energy of the two lasers were 0.55 mJ and 0.29 mJ. The beam quality factor, the energy fluctuation and the time jitter of the 1064 nm laser were 1.58, 0.000063% and 2.18 ps; and that of the 532 nm laser were 1.35, 0.000011% and 1.56 ps.

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This paper presents a systolic bit-parallel multiplier with flexible latency and complexity over GF(2m) using polynomial basis. Via the employment of shift register array and pipeline strategy, the multiplier designed in this paper is able to work pipelining parallel with smaller critical path. A cell which could reach the function of reducing the input operand’s degree by one and add the results of different degrees together is created in this paper. The systolic bit-parallel multiplier can be made of several such cells. Several multipliers which have different latencies and complexities with pipeline strategy are created with further discuss, the comprehensive performances of these designs are estimated with the parameter of area-time. At the end of the page, we compare the systolic bit-parallel multiplier of this paper with a certain number of typical designs these years, the result shows that the design in this paper obtains a comprehensive performance improvement by 70%, 27% and 31%.