No abstract

A duty cycle corrector (DCC) is proposed in this paper. By directly controlling the duty cycle in the clock distribution path, it can work at a frequency as high as 3.5 GHz. The DCC adopts the continuous-time integrator as the duty cycle detector. The output pulse is scaled down according to the input frequency, which reduces the control voltage ripple and expands the minimum operation frequency to 1 MHz. The test chip is fabricated using SMIC 0.18 lm CMOS process. The experiment results show that the frequency range of the input signal was 1 MHz-3.5 GHz, and the duty cycle range of the input signal is from 0.1-99.9%. The peak-to-peak jitter and power dissipation are 33.3 ps and 0.6 mW, respectively, at an operating frequency of 2 GHz.