Power capacitor is one of the key equipments of the high-voltage direct current (HVDC) transmission system. It is also the main noise source difficult to control. Presently in the world, there are none explicit requirement and regulation on the evaluation and measurement of the noise generated by the power capacitor, which has seriously restricted the development of the further research on the noise control in power capacitor. So the research on the noise measurement method and technology has extremely important significance in scientifically evaluating the noise of power capacitor. Power capacitor in HVDC Converter Station under practical conditions has apparent fundamental frequency and rich harmonic frequency components. In order to simulate this condition, a whole condition loaded bridge circuit of noise measurement on power capacitor has been designed and studied. Two arms of the bridge are used to load fundamental frequency and a parallel resonance compensation inductance is used to reduce the fundamental current, while the other two arms are used to load harmonic frequency. The harmonic frequency load power supply composed of harmonic signal generator and power amplifier which can simultaneously load any combination of harmonics under 48th to simulate the various actual working conditions. The tests indicated that the noise spectrum measured under the designed circuit completely accorded with the one in HVDC Converter Station.

For improving launching velocity and efficiency of intercepting plate in active electromagnetic armor protective system, theoretically analyzing the main parameters that determine the change of electromagnetic force. Investigating the system dynamic changes in different pulsed power equipment driving manners. Combining different driving manners, the dynamic working process of the intercepting plate launcher are simulated, that adopting finite element analytic software Ansoft’s transient solution to simulate the dynamic process of intercepting plate. The maximum velocities obtained in the bipolar driving manner and in the single-polar driving manner are 12.61 m/s and 14.00 m/s respectively. Analysis shows that the effect of the electromagnetic force is not only related with the driving manners but also with the materials.

The design of a 0.7~3.8GHz CMOS power amplifier (PA) for multi-band applications in TSMC 0.18-μm CMOS technology is presented. The PA proposed in this paper uses lossy matching network and low Q multistage impedance matching network to improve wideband. To achieve maximum linearity, this PA operates in the Class-A regime. The post-layout simulation results show that the power amplifier achieves 21.9dB of power gain, 22.3dBm of 1dB compression power output at 2GHz. The power adder efficiency (PAE) at gain compression point is 17.8% at 2GHz.