In sub-100 nm nodes, continuously shrinking CD imposes more demanding requirement on wafer planarity to satisfy constrains of diminishing DOF of lithography process. However, due to incoming non-planarity of wafer surface caused by ECP, and inherent removal rate selectivity regarding to dielectric and metal films of CMP slurries, post Cu-CMP topography exhibits strong dependency not only on process conditions, but also on layout pattern of processed wafers. In this paper, such layout pattern-dependency of post Cu-CMP topography was studied with a pre-designed test chip. Post CMP Cu line thickness and area array-height were characterized with respect to metal line width and feature pattern density. Semi-empirical models were built based on multivariate response surface methodology (RSM) to simulate post Cu-CMP surface topography. By applying the developed models, post CMP Cu-line thickness and area array height were predicted across a shot of M1 layer of a typical 40 nm logic product. The prediction is verified by TEM cross section for selected features. Potential risky hotspots were successfully highlighted by the models.

Sub-Resolution-Assist-Feature (SRAF) placement is an essential approach of Resolution Enhancement Technology (RET) [1], especially for technology node below 45nm. A lot of studies show SRAF can help to improve semi-dense and isolated patterns resolution and process window. However SRAF effect to dense pattern is rarely focused. The border line of the dense pattern is an isolated line on the outer direction. SRAF plays an important role not only to the border line, but also to the interior line beside the border line. In this paper, the SRAF effect to the dense pattern was analyzed. SRAF placement optimization experiments were carried out to a dense line pattern. From the experiments result, SRAF space affects the resolution of dense line pattern much more than SRAF width.The best SRAF space value has been recommended through experiment and optical intensity analysis.

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