The surgical removal of lesions is among the most common and effective treatments for atherosclerosis. It is often the only curative treatment option, and the ability to visualize the full extent of atherosclerotic plaque during the operation has major implications for the therapeutic outcome. Fluorescence imaging is a promising approach for the inspection of atherosclerotic plaques during surgery. However, there is no systematic strategy for intraoperative fluorescent imaging in atherosclerosis. In this study, the in situ attachment of a lipid‐activatable fluorescent probe (CN‐N2)‐soaked patch to the outer arterial surface is reported for rapid and precise localization of the atherosclerotic plaque in ApoE‐deficient mouse during surgery. Stable imaging of the plaque is conducted within 5 min via rapid recognition of abnormally accumulated lipid droplets (LDs) in foam cells. Furthermore, the plaque/normal ratio (P/N) is significantly enhanced to facilitate surgical delineation of carotid atherosclerotic plaques. Visible fluorescence bioimaging using lipid‐activatable probes can accurately delineate plaque sizes down to diameters of <0.5 mm, and the images can be swiftly captured within the stable plaque imaging time window. These findings on intraoperative fluorescent imaging of plaques via the in situ attachment of the CN‐N2 patch hold promise for effective clinical applications.

The circulating current among the paralleled solid state transformers (SSTs) originated by the line parameter and mismatched output impedance comes into appearance in the islanded operation of the novel microgrid, the future renewable electric energy delivery and management system. In this regard, the aggregated control strategy of both virtual inductance and external inductance is proposed in this paper to suppress circulating current. The "matching concept" regarding the parameter selection of virtual and external inductance is proposed to ensure the reliable operation of the system through constructing the complete small-signal model of SST. On the basis of aggregated control strategy and small-signal model, the adaptive virtual impedance control strategy is finally proposed by introducing the feedback of circulating current into the conventional virtual impedance control. The virtual impedance is adjusted adaptively according to the judgment algorithm to regulate the equivalent output impedance of SST. With this modification, the adjustment ability of virtual impedance control against sudden disturbance is improved and the circulating current is further reduced. The simulation results with nonlinear loading are presented to prove that the proposed control strategy, and the parameters determined by the matching concept substantially reduce the circulating current among SSTs and improve the accuracy of load sharing among SSTs.

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For triple-level or quad-level 3D NAND flash memory, narrowing the Vth distribution of each state without influencing page program performance is one of the challenges. Considering this challenge, a novel adaptive pulse programming (APP) scheme was proposed. The proposed APP scheme adopted additional verify operations to separate the cells with different programming speed. It enhanced the program effect of slow cells by using increasing programming step voltage, and prevented the fast cells from over programming by using shorter programming pulse width through controlling the voltage of bitline. Compared with general incremental step pulse programming scheme, experimental results on TLC 3D NAND flash showed that, APP scheme could reduce the Vth distribution width of cells by around 15% and at the same time save the program time. Index Terms-3D NAND flash memory, ISPP, 3-bit per cell, Vth distribution I. INTRODUCTION VER the past decade, due to the development of the word line (WL) stacking technology, three-dimension (3D) NAND flash memory has gained an rapidly growing market share in applications of mobile device and solid state drives (SDDs) [1], [2]. In addition, 3-bit/cell (TLC) and 4-bit/cell (QLC) NAND flash memory have become the mainstream of the market, expanding the capacity and reducing the cost of 3D NAND flash significantly [3], [4]. However, for multi-bit per