A two-port capacitorless PNPN device with high density, high speed and low power memory fabricated using standard CMOS technology is presented. Experiments and calibrated simulations were conducted which prove that this new memory cell has a high operation speed (ns level), large read current margin (read current ratio of 10 4 ), low process variation, good thermal reliability and available retention time (190 ms). Furthermore, the new memory cell is free of the cyclic endurance/reliability problems induced by hot-carrier injection due to the gateless structure.

A novel methodology to statistically analyze the statistics on small device performance is presented for the first time. To verify the accuracy of analysis and modeling, TCAD simulation is used to mimic possible process-induced and random fluctuations. The proposed approach precisely decouples various process dependency of the device electric behavior and predicts the device performance trend induced by these variables. 1. Introduction CMOS device variability stimulates more concerns and studies recently as it dramatically increases as device geometry scales down [1]-[5]. Obviously, an accurate statistical model is crucial for both technology development [1]-[3] and circuit/system design [4] [5]. It is required that the model should not only capture the variations and correlations of the electrical behavioral, but also distinguish and predict different process-induced impacts on the performance. For example, as a new process technique is introduced, one wants to not only know whether the change of performance comes from either mobility or parasitic reduction, but also predict the scale of the change as the technique is applied on another established flow.This requirement can be generalized to two questions: 1. how to accurately capture the statistic of the measured data; and 2. what are the variability contributions of different origins: e.g. gate-length edge roughness, oxide thickness variation, random doping fluctuation (RDF), etc. Although many researches have been presented ([1][2][4]) to satisfy the requirement, few show how to decouple the variation. Indeed, there are test structures (such as capacitors arrays to capture gate oxide thickness) used to measure individual process-induced variation trend. However, the variation measured on these test structures are not representative to what are on small devices. Also they cannot be used to extract the trends of implicit variables such as mobility and RDF.The question then is whether one can use a few measured device parameters (e.g. drive currents) and some basic knowledge from device physics to extract the impacts of different process-induced variations, including explicit ones (like gate length, gate dielectric thickness) and implicit ones. Here, we will present a simple technique to extract the correlation between the process-induced or intrinsic variables and measured electrical parameters. Using this method, one can extract an accurate statistics model and gain the insight of the process impact on device performance based on measured data. Statistical Analysis and TheoriesTo establish the link between the process and device performance, one can list a set of measured electrical parameters which strongly depends on (thus will be representative to) one or more possible process-induced variables. Fig. 1 shows the "spider" charts of the correlation coefficients between a set of electrical measured parameters and six process-induced variables, using the TCAD simulation technique described in the following section (similar to [6]). Each axle represents a variab...