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The computation of Global Virtual Time is of fundamental importance in Time Warp based Parallel Discrete Event Simulation Systems. Shared memory multiprocessor architectures can support interprocess communication with much smaller overheads than distributed memory systems. This paper presents a new, completely asynchronous, Gvt algorithm which provides very fast and accurate Gvt estimation with significantly lower overhead than previous approaches. The algorithm presented is able to support more efficient memory management, termination, and other global control mechanismsThe Gvt algorithm described enables any Time Warp entity to compute Gvt at any time without slowing down other entities, in particular, those executing on the critical path. Experimental results are presented f o r a shared memory Tame Warp system that employs a two tiered distributed memory management scheme.The proof of the correctness and the accuracy of the algorithm are also presented. Finally, some suggestions on possible further optimization of the implementation are given.

The design of an ATM Traffic and Network (ATM-TN) simulator which characterizes cell level network behavior is presented. The simulator incorporates three classes of ATM traffic source models: an aggregate ethernet model, an MPEG model and a World Wide Webb transactions model. Six classes of ATM switch architectures ate modeled including output buffered, shared memory buf€ered and cross bar switch models, and then multistage switches which can be built from these three basic models.The ATM-TN simulator can be used to charxterize arbitrary ATM networks with dynamic multimedia traffic loads. Call set up and tear down via ATh4 s i m n g is implemented in addition to the various types of cell traffic streams generated by voice, video and data. The simulator is built on a simple, efficient simulation language called SimKit which is capable of support& both fast sequential and parallel execution. Parallel execution is supported using WarpKit, an optimistically synchronized kemel that is aimed at shared memory multiprocessor platforms such as the Silicon Graphics Powerchallenge and Sun Sparc 1000 series machines.The paper outlines general requirements for ATM W i c and network simulation, presents an ATM-TN simulator architecture, describes its major components and discusses the major issues associated with cell level ATM modeling and simulation.

ADSTRACT The design of an ATM Traffic and Netwo& (ATM-TN) simulator which characterizes cell level network behavior is presented. The simulator incorporates three classes of ATM trat%c source models: an aggregate ethernet model, an MPEG model and a World Wide Webb transactions