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In this paper, we report an on-chip implementation of a Ku-band nanosecond scale time-stretching (TS) system in a 130 nm CMOS process. The system employs a linear chirp generator realized by ramping the control voltage of the voltage controlled oscillator (VCO), a broadband amplitude modulation (AM) circuit and an active dispersive delay line (DDL) improved from a previous integrated DDL, showing 1 ns dispersion over the frequency range from 12 GHz to 16 GHz. This work not only shows the experimental demonstration of the time stretching effect on the pulsed signal, but also indicates the potential for implementation of more complicated time scaling signal processing systems on chip. Index Terms -Time stretching (TS), integrated dispersive delay line (DDL), distributed amplifier (DA), voltage controlled oscillator (VCO), bandpass filter (BPF).

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In this paper, we present a CAD technique to design low-power and low phase noise integrated frequency synthesizers. This technique introduces a key parameter, Phase Noise per Unit Power, which correlates phase noise and power among all the sub-circuits in the frequency synthesizer. By correlating the performance of all the independent circuits together, sophisticated synthesizer design and optimization can be significantly simplified. We demonstrate a 1.8 GHz frequency synthesizer design in a 0.18 lm CMOS process achieving -132 dBc/Hz phase noise at 100 kHz offset with less than 4.3 mW power consumption.

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