No abstract

Abstract-Space-Time Adaptive Processing (STAP) algorithm has recently been used in Passive Bi-static Radars (PBR) because it removes the clutter and non-cooperative transmitter effectively making the target detection easy in harsh environments like air-ground. Realtime implementation of STAP is a very challenging task as it is computationally-intensive, time-critical and resource-hungry process. This paper focuses on the Field-Programmable Gate Array (FPGA) implementation of STAP algorithm for passive radar using FM radio as transmitter of opportunity. The signals of interest were collected using an eight-channel software-defined radar with a uniform circular array (UCA). The STAP processing was simulated using MATLAB and hardware implementation was carried out on a Xilinx Virtex-6 FPGA. The system is tested using experimental radar data. Timing and Power analysis of hardware implementation justifies that FPGA provides a fast and reliable platform for STAP real-time radar processing.