Self-driven photodetectors that can detect light without any external voltage bias are important for low-power applications, including future internet of things, wearable electronics, and flexible electronics. While two-dimensional (2D) materials exhibit good optoelectronic properties, the extraordinary properties have not been fully exploited to realize high-performance self-driven photodetectors. In this paper, a metal–semiconductor–metal (MSM) photodetector with graphene and Au as the two contacts have been proposed to realize the self-driven photodetector. Van der Waals contacts are formed by dry-transfer methods, which is important in constructing the asymmetrical MSM photodetector to avoid the Fermi-level pinning effect. By choosing graphene and Au as the two contact electrodes, a pronounced photovoltaic effect is obtained. Without any external bias, the self-driven photodetector exhibits a high responsivity of 7.55 A W−1 and an ultrahigh photocurrent-to-dark current ratio of ~108. The photodetector also shows gate-tunable characteristics due to the field-induced Fermi-level shift in the constituent 2D materials. What is more, the high linearity of the photodetector over almost 60 dB suggests the easy integration with processing circuits for practical applications.

A fundamental limit for the supply voltage of conventional field-effect transistors is the long high-energy tail of the Boltzmann distribution of the carrier population at the source junction, which requires a gate voltage at least 60 mV to change one decade of current. Here 2D semiconductors are adopted as channel materials and hafnium zirconium oxide (HZO) as negative capacitance (NC) gate stack to realize low-power complementary logic inverter. With HZO/Al 2 O 3 NC gate stack, the 2D semiconductor field-effect transistor (FET) shows an average subthreshold slope less than Boltzmann limit (as low as 18 mV dec −1) at room temperature for both forward and reverse gate voltage sweeps, which allows to reach the same ON-state current at a lower V dd without increasing the OFF-state current. The drain current can be modulated by 5 × 10 4 within 220 mV, still exhibiting average SS below 60 mV dec −1. By constructing van der Waals contact to improve the charge injection and control the carrier type, unipolar p-type WSe 2 FET with reduced hole Schottky barrier height is achieved. The complementary inverter with MoS 2 and WSe 2 NCFETs shows the power consumption of 68 pW.

Ultrathin two-dimensional (2D) semiconductors are regarded as a potential channel material for low-power transistors with small subthreshold swing and low leakage current. However, their dangling bond-free surface makes it extremely difficult to deposit gate dielectrics with high-quality interface in metal-oxide-semiconductor (MOS) field-effect transistors (FETs). Here, we demonstrate a low-temperature process to transfer metal gate to 2D MoS 2 for high-quality interface. By excluding extrinsic doping to MoS 2 and increasing contact distance, the high-barrier height Pt-MoS 2 Schottky junction replaces the commonly used MOS capacitor and eliminates the use of gate dielectrics. The MoS 2 transferred metal gate (TMG) FETs exhibit sub-1 V operation voltage and a subthreshold slope close to thermal limit (60 mV/dec), owing to intrinsically high junction capacitance and the high-quality interface. The TMG and back gate enable logic functions in a single transistor with small footprint.