Low‐Power Complementary Inverter with Negative Capacitance 2D Semiconductor Transistors

Abstract

A fundamental limit for the supply voltage of conventional field-effect transistors is the long high-energy tail of the Boltzmann distribution of the carrier population at the source junction, which requires a gate voltage at least 60 mV to change one decade of current. Here 2D semiconductors are adopted as channel materials and hafnium zirconium oxide (HZO) as negative capacitance (NC) gate stack to realize low-power complementary logic inverter. With HZO/Al 2 O 3 NC gate stack, the 2D semiconductor field-effect transistor (FET) shows an average subthreshold slope less than Boltzmann limit (as low as 18 mV dec −1) at room temperature for both forward and reverse gate voltage sweeps, which allows to reach the same ON-state current at a lower V dd without increasing the OFF-state current. The drain current can be modulated by 5 × 10 4 within 220 mV, still exhibiting average SS below 60 mV dec −1. By constructing van der Waals contact to improve the charge injection and control the carrier type, unipolar p-type WSe 2 FET with reduced hole Schottky barrier height is achieved. The complementary inverter with MoS 2 and WSe 2 NCFETs shows the power consumption of 68 pW.

Fermi‐Level Pinning Free High‐Performance 2D CMOS Inverter Fabricated with Van Der Waals Bottom Contacts

“…Tien Dat Ngo, Zheng Yang, Myeongjin Lee, Fida Ali, Inyong Moon, Dong Gyu Kim, Takashi Taniguchi, Kenji Watanabe, Kang-Yoon Lee, and Won Jong Yoo* DOI: 10.1002/aelm.202001212 MoS 2 , MoSe 2 ) and the other to be p-type metal-oxide-semiconductor (PMOS) (e.g., WSe 2 and BP); [3,6,7] nonetheless, homogeneous structures are preferable to heterostructures due to material uniformity and processing simplicity enabled by the same channel material. In the conventional Silicon (Si) technology, ion implantation has been used as an effective technique for controlling the device polarity (n-type or p-type) and doping concentration; however, the ion implantation cannot be employed effectively on 2D materials due to its atomic ultra-thinness to accommodate substitutional dopant atoms.…”

“…Moreover, 2D van der Waals (vdWs) surface with free dangling‐bonds free layers can be utilized effectively in combining several 2D materials for fabricating devices with diverse functions. [ 3–5 ] Recently, major progress has been made with 2D complementary metal‐oxide‐semiconductor (CMOS) consisting of one to be n‐type metal‐oxide‐semiconductor (NMOS) (e.g., MoS 2 , MoSe 2 ) and the other to be p‐type metal‐oxide‐semiconductor (PMOS) (e.g., WSe 2 and BP); [ 3,6,7 ] nonetheless, homogeneous structures are preferable to heterostructures due to material uniformity and processing simplicity enabled by the same channel material. In the conventional Silicon (Si) technology, ion implantation has been used as an effective technique for controlling the device polarity (n‐type or p‐type) and doping concentration; however, the ion implantation cannot be employed effectively on 2D materials due to its atomic ultra‐thinness to accommodate substitutional dopant atoms.…”

Origins of genuine Ohmic van der Waals contact between indium and MoS2

“…monolayer MoS 2 : χ 1L MoS2 % 4 eV, multilayer MoS 2 : χ ML MoS2 % 4.3 eV) have not been effective because of the strong Fermi-level pinning (FLP) effect 6,7 . While various approaches have been explored to overcome this problem, including molecular doping 8 , tunnel-barrier insertion 9,10 , fabrication of graphene contacts 11,12 , and TMDC phase changes 13 , recent studies have shown that the formation of an ideal or defect-free metal-TMDC van der Waals (vdW) contact through the transfer of atomically flat metal thin films significantly improves the contact properties [14][15][16] . In these advances, it was important to recognize that the conventional thermal evaporation process of metals typically introduces crystalline defects in TMDCs and leads to an uncontrollable ϕ SB (or FLP) and high contact resistance 7,14 .…”

Sub‐Thermionic Negative Capacitance Field Effect Transistors with Solution Combustion‐Derived Hf0.5Zr0.5O2

“…The performance of previously reported NCFETs is presented in Table S4, Supporting Information. [11,21,22,[51][52][53][54][55][56][57] However, a solution-processed HZO was fabricated using a simple solution formulation method using combustion chemistry for the first time.…”