Psoriasis is an autoimmune disease, which is characterized by aberrantly high levels of inflammation, but the underlying pathogenic mechanisms are still not fully understood. Signal transducer and activator of transcription 1 (STAT1) and STAT3, and the downstream proteins suppressor of cytokine signaling 1 (SOCS1) and SOCS3, have been implicated in psoriasis disease progression. Calcipotriol, a synthetic derivative of vitamin D, has been used clinically to treat psoriasis, but the mechanism of action that underlies the beneficial effects of calcipotriol is still being explored. The objective of this study was to determine whether STAT1 and STAT3 signaling is involved in calcipotriol treatment. Using an in vitro immortal human keratinocyte cell line, HaCaT cells, as a psoriasis model, we examined the molecular signaling induced by calcipotriol treatment. We found that calcipotriol treatment or silencing of either STAT1 or STAT3 inhibited proliferation of HaCaT cells. Calcipotriol downregulated the expression of STAT1 and STAT3 at the messenger RNA (mRNA) and protein levels. The levels of phosphorylated STAT1 and STAT3 were also decreased, suggesting calcipotriol treatment inhibited STAT1 and STAT3 activation. Calcipotriol-mediated STAT inhibition was further substantiated by the downregulation of SOCS1 and SOCS3 at the mRNA and protein expression levels. Taken together, our results suggest a novel molecular mechanism for calcipotriol-mediated treatment effects in psoriasis.

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In this article, we present a reusable Java processor IP for application processors of embedded systems. For the Java microarchitecture, we propose a low-cost stack memory design that supports a two-fold instruction folding pipeline and a low-complexity Java exception handling hardware. We also propose a mapping between the Java dynamic class loading model and the SoC platform-based design principle so that the Java core can be encapsulated as a reusable IP. To achieve this goal, a two-level method area with two on-chip circular buffers is proposed as an interface between the RISC core and the Java core. The proposed architecture is implemented on a Xilinx Virtex-5 FPGA device. Experimental results show that its performance has some advantages over other Java processors and a Java VM with JIT acceleration on a PowerPC platform.