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In this paper, a discrete non-stationary multiple-input multiple-output (MIMO) channel model suitable for the fixed-point realization on the field-programmable gate array (FPGA) hardware platform is proposed. On this basis, we develop a flexible hardware architecture with configurable channel parameters and implement it on a non-stationary MIMO channel emulator in a single FPGA chip. In addition, an improved non-stationary channel emulation method is employed to guarantee accurate channel fading and phase, and the schemes of other key modules are also illustrated and implemented in a single FPGA chip. Hardware tests demonstrate that the output statistical properties of proposed channel emulator, i.e., the probability density function (PDF), cross-correlation function (CCF), Doppler power spectrum density (DPSD), and the power delay profile (PDP) agree well with the corresponding theoretical ones.

In this paper, a discrete non-stationary multipleinput multiple output (MIMO) channel model based on the sum of linear frequency modulation (SoLFM) method is proposed. The new model is suitable for generating non-stationary fading with continuous phase and accurate Doppler frequency. In order to implement the proposed model with large-scale antennas by fieldprogrammable gate array (FPGA) platform, an efficient coordinate rotation digital computer (CORDIC) method is proposed. By introducing a full parallel pipeline architecture, rotation factor state, and domain folding technique, the new generator can significantly reduce the hardware resource usage and meet the requirement of large-scale channel emulation. The measurement and analyze results show that the statistical properties, i.e., the probability density function (PDF) and autocorrelation function (ACF) of generated channels provide a good agreement to the theoretical ones.

A wireless channel digital twin is a useful tool to evaluate the performance of a communication system at the physical or link level by generating the physical channel controllably. In this paper, a stochastic general fading channel model is proposed, which considered most of the channel fading types for various communication scenarios. By using the sum-of-frequency-modulation (SoFM) method, the phase discontinuity of the generated channel fading was well addressed. On this basis, a general and flexible generation architecture for channel fading was developed on a field programmable gate array (FPGA) platform. In this architecture, improved CORDIC-based hardware circuits for the trigonometric function, exponential function, and natural logarithm were designed and implemented, which improved the real-time performance of the system and the utilization rate of the hardware resources compared with the traditional LUT and CORDIC method. For a 16-bit fixed-point data bit width single-channel emulation, the hardware resource consumption was significantly reduced from 36.56% to 15.62% for the overall system by utilizing the compact time-division (TD) structure. Moreover, the classical CORDIC method brought an extra latency of 16 system clock cycles, while the latency caused by the improved CORDIC method was decreased by 62.5%. Finally, a generation scheme of a correlated Gaussian sequence was developed to introduce a controllable arbitrary space–time correlation for the channel generator with multiple channels. The output results of the developed generator were consistent with the theoretical results, which verified the correctness of both the generation method and hardware implementation. The proposed channel fading generator can be applied for the emulation of large-scale multiple-input, multiple-output (MIMO) channels under various dynamic communication scenarios.

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