The scaling down of CMOS technology has been carried out successfully following the Moore’s law for the last five decades. One of the main challenges for a nano scaled device are the Short Channel Effects (SCEs). It has begun to reach the limit of Silicon material; hence high-k dielectric materials are introduced to challenge the SCEs. Particularly HfO2 is used for this study. The high k dielectric material has been compared with the well-known SiO2 in a 3D SOI Tri-Gate (TG) FinFET device which is modelled and simulated in SILVACO TCAD tools. TG SOI FinFETs having 22nm,14nm and 10 nm channel lengths are developed. Since the device are in nano regime, short channel device parameters such as threshold voltage, subthreshold swing (SS), Ion current, Ioff current, Ion/Ioff ratio and DIBL are analysed for the two materials developed in TG SOI FinFET. The comparison shows that high k dielectric materials shows better results in reducing current leakage and drain induced barrier leakage than that of SiO2.

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