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In this paper, we investigate the electrical behavior of TSV with increasing temperatures (25-150 o C). TSV capacitance, leakage current and TSV resistance with varying temperatures are reported. TSV C-V characteristics are analyzed to extract the oxide charges. It is confirmed that the depletion behavior of TSV can be exploited to reduce TSV capacitance even at higher temperatures. In addition, lumped RC model of the TSV for circuit simulations is enhanced by incorporating measured TSV resistance and capacitance change due to temperature. The results are corroborated with the 2D/3D Ring Oscillator (RO) measurements at different temperatures. IntroductionThree-dimensional (3-D) ICs are promising to keep pace with Moore's law in the forthcoming decade. In addition to FEOL transistors and BEOL interconnects, Through Silicon Via (TSV) forms an integral component of 3-D ICs. Functional 3D circuits in 130nm technology obtained by a 3D stacked IC approach using both, TSV First and cost effective solution Die-to-Wafer Hybrid Collective bonding have already been demonstrated by IMEC [1][2][3][4][5]. The densely packed transistor arrays in contemporary 3-D ICs render higher operating temperatures [6]. Because of elevated temperatures the performance of 3-D circuit elements becomes increasingly important and hence require high temperature characterization of 3-D circuit elements.Various schemes to exploit the depletion behavior of the silicon substrate to reduce the TSV capacitance have already been reported [7]. The depletion behavior of silicon can also be exploited by tailoring the oxide charges during the TSV process [8]. But, it remains to be seen if the depletion behavior of silicon could still be exploited at elevated operating temperatures or not. Hence, the effect of temperature on the TSV C-V characteristics is of increasing interest. This paper focuses on the high temperature characterization of TSV capacitance, leakage and resistance. High temperature performance of 2D/3D ROs is also analyzed and is correlated to the rise of TSV capacitance at higher temperatures.