In this work, we investigate the impact oflayout shapes on STI stress. Based on a stress simulator developed by us, we propose analytical models to correlate the STI stress and the layout parameters. Our model is validated by data collectedfrom a commercial 65nm process. The experimental results prove that the device characteristics predicted by our model closely match the measured data.Process simulators such as Taurus provide results with a high accuracy. However, they actually cannot consider the distribution of the STI stress of 2-D layout. Accordingly, we develop a new stress simulation tool [11], which is calibrated by Taurus simulation results on simple layout shapes. Using a finite element method, our stress simulator considers major stress sources, such as thermal mismatch, intrinsic stress, growth of materials and viscoelasticity, to perform highfidelity simulation of the STI stress. Fig. 2 shows a small Fi~. 1. Layout parameters related to STI stress stress distribution can be used to calibrate our stress simulator. With the stress simulator, the relation between the STI stress distribution and layout parameters can be studied in detail. Then we provide analytical models that could capture the impact of STI stress induced by arbitrary layout shapes. Finally we validate our model by applying it to analyze the subthreshold leakage current in 65nm technology.