0.18um BCD technology with best-in-class LDMOS from 6 V to 45 V

Huang, Tsung–Yi; Liao, Wen-Yi; Yang, Ching-Yao; Huang, Chien‐Hao; Yeh, Wang-Chi Vincent; Huang, Chih-Fang; Lo, Kuo-Hsuan; Chiu, Chien-Wei; Kao, Tzu-Cheng; Su, Hung-Der; Chang, Kuo-Cheng

doi:10.1109/ispsd.2014.6856005

Cited by 15 publications

(4 citation statements)

References 4 publications

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“…The grey line is Ref. [7][33][34] [35] devices with conventional field plates as well, these data is at similar level, and we put them together into one group. Fig.…”

Section: Bfom Resultsmentioning

confidence: 99%

Design and Simulation Optimization of an Ultra-Low Specific On-Resistance LDMOS Device

Yu,

Shao,

Chen

et al. 2024

IEEE J. Electron Devices Soc.

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The design of LDMOS (Lateral double diffused metal oxide semiconductor) devices with CFP (Contact field plate) has been of great significance in recent years, according to its advantages of low resistance and high switch efficiency. In this paper, this ultra-low , (Specific on-resistance) LDMOS device is simulated, designed, and fabricated. The effects on FOM (Figures-of-merits) characters from physical dimensions, including field plate length L, field plate thickness H, and slot contact width W, have been analyzed and discussed. The best device structure is proposed through simulation, and a related fabrication process is introduced correspondingly. Finally, the electrical measurement results show that , can achieve as low as 6.9m•mm 2 when the source-drain (Breakdown voltage) arrives at 34.1V, which is improved by 47.1% compared with conventional devices. Furthermore, the TLP (Transmission line pulse) test results indicate that the device owns an ideal SOA (Safe operation area) from both typical devices (W=10 m) and very large devices (W= 2mm). Index Terms-Contact field plate (CFP), Figures of merits (FOM), Lateral double diffusion metal oxide semiconductor (LDMOS), Specific on-resistance ( , )

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“…The grey line is Ref. [7][33][34] [35] devices with conventional field plates as well, these data is at similar level, and we put them together into one group. Fig.…”

Section: Bfom Resultsmentioning

confidence: 99%

Design and Simulation Optimization of an Ultra-Low Specific On-Resistance LDMOS Device

Yu,

Shao,

Chen

et al. 2024

IEEE J. Electron Devices Soc.

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“…Wafer-level electrical data is collected with Agilent B1500 tools. For comparison, five different devices are measured, including [18] FAB-350 nm, [19] FAB-130 nm, [20] FAB-180 nm, and Can.-FAB-153 nm fabricated with process conditions from Group 1 and Group 4, respectively.…”

Section: Electrical Resultsmentioning

confidence: 99%

A Process Optimization Method of the Mini-LOCOS Field Plate Profile for Improving Electrical Characteristics of LDMOS Device

Yu,

Shao,

Gao

et al. 2023

IET Circuits, Devices & Systems

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In this work, the effects of the mini-local oxidation of silicon (LOCOS) field plate’s bottom physical profile on the devices’ breakdown performance are analyzed through technology computer-aided design simulations. It is indicated that the “abrupt” bottom profile could certainly do with an optimization. This paper introduces an effective process improvement method by etching bias power adjustment and time reduction. The upgradation of the field plate physical profile has been proved by transmission electron microscope cross-section analysis. The angle for the bottom surface of mini-LOCOS field plate θ2 is improved from 11.9° to 12.6°, and the thickness ratio of Hup/Hbottom (field plate oxide thickness for the upper and bottom, respectively) is increased from 71.8% to 76.6%. Finally, the optimized laterally diffused metal oxide semiconductor devices have been fabricated, and both figure of merit curves and safe operation area curves are measured. The specific on-resistance Ron,sp could achieve as low as 11.3 mΩ mm2, while breakdown voltage BVds,max arrives at 37.4 V, which is nearly 19.3% improved.

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“…With the increase of demand for more complex and faster logic function in analog power IC, it is significant to improve the performance of the lateral double-diffused metal-oxide-semiconductor transistor (LDMOS), specially minimizing specific on-resistance (R on,sp ) and maximizing off-state breakdown voltage (BV) [1][2][3][4][5][6][7][8][9]. Most developed technologies focus on the drift region optimizing to improve the trade-off of R on,sp vs. BV for LDMOS devices [10][11][12][13][14][15][16][17][18][19][20].…”

Section: Introductionmentioning

confidence: 99%

Ultra-Low Specific On-resistance Lateral Double-Diffused Metal-Oxide-Semiconductor Transistor with Enhanced Dual-Gate and Partial P-buried Layer

et al. 2019

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An ultra-low specific on-resistance (Ron,sp) lateral double-diffused metal-oxide-semiconductor transistor (LDMOS) with enhanced dual-gate and partial P-buried layer is proposed and investigated in this paper. On-resistance analytical model for the proposed LDMOS is built to provide an in-depth insight into the relationship between the drift region resistance and the channel region resistance. N-buried layer is introduced under P-well to provide a low-resistance conduction path and reduce the resistance of the channel region significantly. Enhanced dual-gate structure is formed by N-buried layer while avoiding the vertical punch-through breakdown in off-state. Partial P-buried layer with optimized length is adopted under the N-drift region to extend vertical depletion region and relax the electric field peak in off-state, which enhances breakdown voltage (BV) with low drift region resistance. For the LDMOS with enhanced dual-gate and partial P-buried layer, the result shows that Ron,sp is 8.5 mΩ·mm2 while BV is 43 V.

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0.18um BCD technology with best-in-class LDMOS from 6 V to 45 V

Cited by 15 publications

References 4 publications

Design and Simulation Optimization of an Ultra-Low Specific On-Resistance LDMOS Device

Design and Simulation Optimization of an Ultra-Low Specific On-Resistance LDMOS Device

A Process Optimization Method of the Mini-LOCOS Field Plate Profile for Improving Electrical Characteristics of LDMOS Device

Ultra-Low Specific On-resistance Lateral Double-Diffused Metal-Oxide-Semiconductor Transistor with Enhanced Dual-Gate and Partial P-buried Layer

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