0.45-V operating V&lt;inf&gt;t&lt;/inf&gt;-variation tolerant 9T/18T dual-port SRAM

Noguchi, Hiroki; Okumura, Satoshi; Takagi, Tomoya; Kugata, Koji; Yoshimoto, Masahiko; Kawaguchi, Hiroshi

doi:10.1109/isqed.2011.5770728

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T Comparison Sram Structure and Its Application1

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2011

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“…The 7T bitcells in a pair mutually connect their internal nodes using pMOS transistors. The 7T/14T bitcell and its applications are researched previously [5][6][7]. The 7T/14T dependable SRAM can improve the reliability when one bit datum is stored in the two bitcells.…”

Section: T Comparison Sram Structure and Its Applicationmentioning

confidence: 99%

Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancy

Okumura

Nakata

Yanagida

et al. 2011

2011 IEEE Custom Integrated Circuits Conference (CICC)

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This paper proposes a 7T SRAM that realizes a block-level instantaneous comparison feature. The proposed SRAM is useful for operation results comparison in dual modular redundancy (DMR). The data size that can be instantaneously compared is scalable using the proposed structure. The 1-Mb SRAM comprises 16-kb blocks in which 8-kb data can be compared in 130.0ns. The proposed scheme reduces power consumption in data comparison by 92.3%, compared to that of a parallel cyclic redundancy check (CRC) circuit.

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Section: T Comparison Sram Structure and Its Applicationmentioning

confidence: 99%