0.6–2.7-Gb/s Referenceless Parallel CDR With a Stochastic Dispersion-Tolerant Frequency Acquisition Technique

Han, Jinho; Won, Hyosup; Bae, Hyeon‐Min

doi:10.1109/tvlsi.2013.2268862

Cited by 9 publications

(6 citation statements)

References 10 publications

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“…With the continuous expansions of the applications of wired serial communication, the performance, cost, and scalability of clock and data recoveries (CDRs) as the core component of wireline receivers are getting more attention. Referenceless CDRs have the following advantages over existing CDRs that requires a reference clock: First, the operational data rate being neither fixed nor of a few predefined values, a referenceless CDR can adaptively operates at any data rate within the tuning range of DCO [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19]. Therefore, it has a wider range of applications and improves the reusability of IPs.…”

Section: Introductionmentioning

confidence: 99%

All-digital half-rate referenceless CDR with single direction frequency sweep scheme using asymmetric binary phase detector

Park

Huang

et al. 2020

IEICE Electron. Express

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This paper presents an all-digital half-rate referenceless CDR with a single direction frequency acquisition achieved. Thanks to asymmetric binary phase detector (ABPD), compared with existed inverse alexander phase detector (IAPD), we changed the input-output characteristic to enable accumulated phase error point in the same direction when frequency error happens while the output of IAPD has no directivity. Once the frequency of the digital controlled oscillator (DCO) enters the pull-in range of the CDR loop, the phase is automatically locked. To improve jitter tolerance (JTOL) performance further, IAPD logic is enabled, and ABPD is disabled after locking. The prototype was implemented in a 28 nm low power CMOS process with a data rate tracking range of 9-11 Gb/s. The measured JTOL is 0.35 UI at high frequency with PRBS31 input data pattern.

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Section: Introductionmentioning

confidence: 99%

All-digital half-rate referenceless CDR with single direction frequency sweep scheme using asymmetric binary phase detector

Park

Huang

et al. 2020

IEICE Electron. Express

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“…The referenceless CDR satisfies this requirement. The referenceless CDR [3][4][5][6][7][8][9][10][11][12][13][14][15][16] extracts the clock signal from the received data signal alone without using any reference clock sources ( Fig. 1(b)).…”

Section: Introductionmentioning

confidence: 99%

“…This method is limited to a specific encoding scheme, such as the 2 7 -1 PRBS data for [8] and the 8B10B-encoded data for [9]. The third solution recovers the clock signal by using the randomness of input data [10][11][12][13]. The input data stream is divided by more than 1000 and the resultant output is applied to a frequency multiplier to recover the clock signal.…”

Section: Introductionmentioning

confidence: 99%

An Adaptive-Bandwidth Referenceless CDR with Small-area Coarse and Fine Frequency Detectors

Kwon¹,

Lim²,

Kim³

et al. 2015

JSTS:Journal of Semiconductor Technology and Science

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“…However, we use two VCO loops, which are placed on both sides of the channels, to minimize clock-path length. Minimum clock-path length enables a full-rate frequency loop, which has lower jitter compared to the frequency loop using frequency-divided signals [3]. We realize the full-rate loop with Pottbacker phase-frequency detector [4].…”

mentioning

confidence: 99%

“…Because the VCO loop can act as only a coarse tune, the PI loop needs fast response corresponding to the frequency mismatch between the VCO clocks and data. Compared to the digital type PI loops [3,6], the analog type PI loop is advantageous for achieving high-speed operation. (c) shows our PI and control architecture to generate the recovered clock.…”

mentioning

confidence: 99%

22.8 A 24-to-35Gb/s x4 VCSEL driver IC with multi-rate referenceless CDR in 0.13um SiGe BiCMOS

Tsunoda

Shibasaki

Ide

et al. 2015

2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers

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The optical interconnect technologies are a promising solution for high-speed and high-density interconnects because of the high-bandwidth and low-crosstalk properties of optical signals. The next challenge for optical interconnects is to move to a serial data-rate of 25Gb/s or higher [1,2]. To achieve flexible interconnects on a bandwidth demand, a CDR is required to operate at multiple rates in a wide tuning range. A selectable multi-VCO structure is one method to overcome this issue. However, when multi-VCOs are allocated in each channel, the large size of VCOs makes it difficult to achieve a high-density optical link. In this paper, we present a dual-loop hybrid CDR including a phase interpolator (PI) loop for phase tracking and a common VCO loop situated outside the channel areas for frequency acquisition. We develop a quadrant-switching analog PI-loop that has the ability to track the frequency mismatch corresponding to full-rate frequency up to 35Gb/s. The 4-channel driver IC with this dual-loop hybrid CDR is fabricated in 0.13μm SiGe BiCMOS technology. With these circuits, we achieve a driver IC with a multi-rate, ranging from 24 to 35Gb/s, reference-less CDR for flexible optical interconnects. Figure 22.8.1 shows a block diagram of VCSEL driver IC with dual-loop, hybrid CDR, which consists of 4-channel PI-loops for retiming the data and common VCO loops for realizing the reference-less operation. A dual-loop architecture allows us to keep a channel pitch of 250μm and to minimize the increase in datapath length, while enabling a multi-clock rate because large LC-QVCOs can be placed outside of the channels. The PI-loop uses quadrature clocks (CKI and CKQ) and rotates the clock phase in the analog PI according to the input data for data retiming. The VCO loop is applied to realize frequency acquisition in reference-less operation. One VCO loop is enough for the operation because there is no frequency difference in the 4 channels. However, we use two VCO loops, which are placed on both sides of the channels, to minimize clock-path length. Minimum clock-path length enables a full-rate frequency loop, which has lower jitter compared to the frequency loop using frequency-divided signals [3]. We realize the full-rate loop with Pottbacker phase-frequency detector [4]. AND-type quadrature LC-VCOs (LC-QVCO) [5] are employed for low phase noise. We implement three different QVCOs that are manually selectable to realize multi-rate capability, supporting three frequency ranges: 24 to 28GHz, 28 to 32 GHz, and 32 to 35GHz.The PI loop is required for high-speed operation and acts in a more dominant fashion than the VCO loop to realize dual loop. Because the VCO loop can act as only a coarse tune, the PI loop needs fast response corresponding to the frequency mismatch between the VCO clocks and data. Compared to the digital type PI loops [3,6], the analog type PI loop is advantageous for achieving high-speed operation. Figure 22.8.2(a) shows a detailed block diagram of the developed quadrature switching analog PI-loop, wh...

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0.6–2.7-Gb/s Referenceless Parallel CDR With a Stochastic Dispersion-Tolerant Frequency Acquisition Technique

Cited by 9 publications

References 10 publications

All-digital half-rate referenceless CDR with single direction frequency sweep scheme using asymmetric binary phase detector

All-digital half-rate referenceless CDR with single direction frequency sweep scheme using asymmetric binary phase detector

An Adaptive-Bandwidth Referenceless CDR with Small-area Coarse and Fine Frequency Detectors

22.8 A 24-to-35Gb/s x4 VCSEL driver IC with multi-rate referenceless CDR in 0.13um SiGe BiCMOS

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