0.6‐V CMOS cascode OTA with complementary gate‐driven gain‐boosting and forward body bias

Cellucci, Danilo; Centurelli, Francesco; Stefano, Valerio Di; Monsurrò, Pietro; Pennisi, S.; Scotti, Giuseppe; Trifiletti, Alessandro

doi:10.1002/cta.2703

Cited by 23 publications

(16 citation statements)

References 18 publications

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“…It can be observed that this design intimates an impressive improvement in FOM SR and g UGB, which allows a more expedient trade-off between speed, power, and load in [28]. This work also exhibits more remarkable small-signal driving ability than [26,[29][30][31][33][34][35] though lower than [27,28,32].…”

Section: Discussion and Comparisonmentioning

confidence: 80%

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An ultra-low-power near rail-to-rail pseudo-differential subthreshold gate-driven OTA with improved small and large signal performances

Ghosh

Bhadauria

2021

Analog Integr Circ Sig Process

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An efficient architecture of a high-performance ultra-low-voltage gate-driven two-stage pseudo-fully differential operational transconductance amplifier (OTA) is presented. The proposed subthreshold-region operated OTA utilizes two identical conventional current-mirror-based source coupled pseudo-differential amplifiers with their cross-connected gate as core amplifier blocks. The input core differential pair exploiting forward body terminal biasing scheme at output load employed in cascaded stages essentially improves the overall transconductance more than twice compared to the conventional pseudo-differential pair based OTA and achieves near rail-to-rail output voltage swing (90.2% of supply voltage) for near rail-to-rail input common-mode voltage (94.92% of supply voltage). The circuit is designed and optimized using g m /I D technique associated with the Particle Swarm Optimization (PSO) algorithm with a single supply of 0.35 V for a capacitive load of 10 pF and simulated in Cadence Virtuoso analog environment using UMC 180-nm CMOS technology. Post-layout simulations have been accomplished to justify the performance of the proposed OTA. It achieves an open-loop gain of 83.00 dB, phase margin of 61.48°, and power dissipation of 35.04 nW at a unity gain frequency of 24.78 kHz. A low-frequency continuous second-order G m -C filter is also implemented to validate its workability. Simulation results of this work are compared to the state-of-the-art architecture available, and enhanced performance is validated. Keywords Operational transconductance amplifier (OTA) Á Unity gain frequency (UGF) Á Subthreshold region Á Input common-mode range (ICMR) Á Biquad G m -C filter & Sougata Ghosh

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Section: Discussion and Comparisonmentioning

confidence: 80%

“…Layout area occupation is also identical with low-power reported solutions. Therefore, two traditional figures of merit (FOM) [14,31] shown in Eqs. (49) and (50) , for small-signal performance and largesignal performance evaluation, respectively, are embraced to compare the OTA's dynamic performances under inspection.…”

Section: Discussion and Comparisonmentioning

confidence: 99%

An ultra-low-power near rail-to-rail pseudo-differential subthreshold gate-driven OTA with improved small and large signal performances

Ghosh

Bhadauria

2021

Analog Integr Circ Sig Process

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“…FOM1 and FOM2 results of the all circuits are visually illustrated in Figures 14 and 15, respectively. Considering the FOM1 results, it is apparently seen that the proposed circuit outperforms the all other circuits, where the FOM1 score of it is 2816 while the runner-up [27] has a FOM1 of 920. Regarding the FOM2 results, the proposed circuits exhibits quite good performance (the runner-up with 730 FOM2 score) that is close to the best score (1170) achieved by [25].…”

Section: Discussionmentioning

confidence: 94%

Low Power-High Gain Bulk-Driven 3 Stages CMOS Miller OTA in 130nm Technology

Afacan

2020

Sakarya University Journal of Science

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The requirement of low-power analog circuits has been raised in recent years due to the strict limitation of power consumption in modern applications. Therefore, the trend in analog circuit design has been changed such that they are able to meet the required specifications with lower power dissipation. Design of low power operational transconductance amplifiers, which are the main building blocks in many analog applications, has been more pronounced to keep the power dissipation below certain levels. In this concern, this study presents a low power, highperforming bulk-driven 3 stages CMOS OTA in a 130 nm standard CMOS technology. The proposed circuit leverages the bulk-driven architecture at the input stage; thus it can operate under sub 1-V. The design process of the proposed OTA is explained in detail and the results are validated via post-layout simulations. The proposed OTA is powered by ±0.45 V symmetric voltage sources, where the power consumption is around 27 μW. The area overhead is only 0.0017 μm2. The open-loop gain, unity gain frequency, and the phase margin are 73.24 dB, 5.167 MHz, and 78 o , respectively. To demonstrate the performance of the proposed circuit, a comparison is made with other circuits published in the last five years considering the well-known figures of merit (FOMs). Comparison results indicate that the proposed solution outperforms the other circuits for small-signal operation while it is the runner-up for large-signal operation.

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“…Over the past decades, their design procedures have faced with the technology scaling mainly imposed by the digital trend predicted by the Moore's law. The reductions of the supply voltage ( DD < 1 V) and of the transistor intrinsic gain ( ∼ 10) pushed the scientific community towards the design of multistage amplifiers where the metric used to evaluate 'speed' performance of OTAs has mainly remained the gain-bandwidth product [1]- [8].…”

Section: Introductionmentioning

confidence: 99%