An innovative low-voltage low-power complementary metal-oxidesemiconductor (CMOS) gain boosting approach is presented. It exploits complementary gate-driven gain boosting and adopts forward body bias, resulting in the minimum possible supply requirement of one threshold plus two saturation voltages, without requiring any additional current branch. The solution is also exploited in a rail-to-rail high-performance single-stage cascode operational transconductance amplifier (OTA). Simulations using a 40-nm process with thresholds around 0.45 V show that 0.6 V and 50 μA are adequate to supply the designed OTA, which exhibits a 60-dB direct current (DC) gain, a 45-MHz unity-gain frequency, and an 18-V/μs slew rate, under a 1-pF load.

The static power consumption in modern integrated circuits has become a critical standpoint in side-channel analysis. As it has been widely demonstrated in the technical literature, it is possible to extract secret information from a cryptographic circuit by means of static current measurements. Static and dynamic power analysis require different measurement procedures, due to physical reasons. In this work, we present a novel measurement setup, which aims to overcome several issues in measuring static currents, such as extremely low SNR and temperature dependency, providing a low-cost solution to carry out Attacks Exploiting Static Power (AESP). The proposed measurement setup is based on a DC pico-ammeter, which allows to acquire DC currents after a long integration time, and on a thermal feedback loop exploiting a commercial Peltier cell to set and control the working temperature of the cryptographic processor. To verify the effectiveness of the proposed setup, AESP have been successfully implemented on a 4�4 bit crypto-core, extracted from a bit slice implementation of the PRESENT-80 algorithm and implemented on a 45nm Xilinx Spartan-6 FPGA