0.6 μm BiCMOS technology for RF and high speed converter applications

Abstract

This paper describes how a state of the art successfu~'y incorporated into a 0'6um process' The circuits or cells designed on either process can be realized on the new process.ple where possible the interaction of the CMOS devices with the bipolar devices. For example, neither the MOS gate for the polysilicon layers of the bipolar transistor as all these cies and sheet resistances. To combine these would require an unacceptable level of compromise on device paramebipolar process designed for R F applications has been po~ysi~icon nor the top capacitor polysilicon were used resultant BiCMoS process has the feature that products, po~ysi~icon layers are incompatible in terms of dopant spe-

EP120: A 0.35um, 3V/5V, Mixed-Signal/RF BiCMOS Technology

“…To compare the performance of 0.35um BiCMOS with the previous generation [5], a PLL frequency was fabricated on both processes. The synthesiser includes a dualmodulus prescaler with selectable frequency divisions of 8/9, 16/17, 32/33, or 64/65.…”

“…The key BiCMOS advantages of low noise, high speed NPNs, plus, low power, dense logic are particularly attractive for mobile RF products. However, BiCMOS is also used extensively in other markets such as highspeed analog, data converters and a wide range of mixed-signal products [5].…”

Dose Loss and Defect Mechanisms in Antimony Buried Layers for a 0.35um BiCMOS Process

“…In this work a defect free Sb BL process is taken from a 0.6um BiCMOS process [1] as a starting point. 2D process simulation using ATHENA [2] is carried out to examine this BL on a 0.35um NPN as shown in Figure 1.…”