0.7–1.8 GHz multiband digital polar transmitter using watt-class current-mode class-D CMOS power amplifier and digital envelope modulation technique for reduced spurious emissions

Abstract

A polar transmitter driven by digital input signals for envelope and phase is demonstrated, using a band-switching output resonator to achieve multiband operation. A new digital pulse width modulation algorithm is also shown to partially suppress spurious signals associated with the digital input envelope signal. The transmitter consists of a current-mode class-D (CMCD) CMOS power amplifier (PA), together with a buck converter with a dead-time generator for improved efficiency. The CMCD PA is tuned by band-switching capacitors that can handle up to 9 V, and is measured to have approximately 30 dBm output power with 31–35% drain efficiency under single-tone testing. The proposed spurious signal reduction technique works to partially suppress quantization noise without increasing power consumption. Overall efficiencies of 27.1/25.6% are obtained at 30.2/28.9 dBm continuous wave (CW) output powers and 0.85/1.75 GHz carrier frequencies, respectively. Spur suppression of 9–10 dB peak is achieved when the proposed algorithm is applied with wideband code division multiple access (WCDMA) modulation.

A State-of-the-Art Review on CMOS Radio Frequency Power Amplifiers for Wireless Communication Systems

“… Linear PAE across linear output power for the proposed linearity enhancement techniques [ 116 , 118 , 119 , 121 , 123 , 124 , 129 , 132 , 133 , 134 , 135 , 136 , 137 , 142 , 143 , 144 , 145 , 146 , 147 , 148 , 149 , 150 ]. …”

“…A polar transmitter with a current-mode class D CMOS PA was presented by T. Nakatani et al ( 2013). This polar transmitter also consisted of a digital pulse width modulation (DPWM) algorithm that was employed to mitigate spurious signals linked with the digital input signal envelope [118]. DPMW was mainly employed to minimize the noises In the polar feedback technique, a local oscillator and a mixer are employed to attenuate and downconvert the output signal of the PA.…”

“…Figure 25. Linear PAE across linear output power for the proposed linearity enhancement techniques[116,118,119,121,123,124,129,[132][133][134][135][136][137][142][143][144][145][146][147][148][149][150].…”

A Cmos Power Amplifier Using a Balun Embedded Driver Stage for Ieee 802.11N Wlan Applications

“…However, recently, CMOS power amplifiers are under vigorously study in hopes of reducing the overall unit cost of production of RF systems [7][8][9][10][11][12][13][14]. One of the many advantages of the CMOS power amplifier is that it can be integrated with digital control blocks and analog circuits to complete a fully integrated SoC [15,16]. Although the linearity and breakdown voltage of CMOS amplifiers are lower than those of HBT amplifiers, various techniques to overcome the weaknesses of the CMOS process have been studied.…”