In this work, we design a linear CMOS power amplifier with a spiral‐type output transformer for IEEE 802.11n WLAN applications. We conduct studies to identify the proper output transformer and power stage structures for linear CMOS power amplifiers. The power amplifier is composed of a single differential‐pair for the power stage to mitigate the stability problems that frequently arise in high gain linear power amplifiers. Additionally, we investigate the output matching network using a spiral‐type output transformer to minimize the output return loss. To verify the feasibility of the power amplifier, we designed a 2.4‐GHz power amplifier with a 180‐nm SOI CMOS process. The designed power amplifier is measured using an IEEE 802.11n WLAN signal. The power amplifier achieves 21.28 dBm output power while the measured EVM satisfies the standard for 802.11n applications. © 2017 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:546–550, 2017

A series electrostatic discharge (ESD) diode structure is proposed to minimise the degradation induced by thermal interaction between series connected diodes. The proposed series diode is constructed using a distributed cell-based ESD diode. To verify the feasibility of the proposed structure, single and series diodes are designed using the typical and the proposed structures. From the experimental results, it is proved that the ESD survival levels of the proposed series diode are nearly identical to those of the single diode, unlike the case of typical series diodes.

In this study, we design a differential CMOS power amplifier using a 180-nm SOI RFCMOS process for 802.11n (64-QAM, 20 MHz bandwidth, 9.6 dB peak to average power ratio (PAPR)) applications. To minimize the chip area and mismatch in differential signals, we propose a layout method with an inter-stage matching network using a split inductor. By virtue of the symmetrical layout of the proposed split inductor, the mismatch in the differential signals is minimized, while the interconnection lines between the driver and power stages are shortened to minimize the overall chip area and the loss induced by the resistive parasitic components. The designed power amplifier is measured using a wireless local area network (WLAN) 802.11n signal to verify the feasibility of the proposed layout technique. The power amplifier achieved 20.34 dBm output power, while the measured EVM for the 802.11n applications is satisfied. From the measured results, we successfully prove the feasibility of the proposed power amplifier.

In this work, we propose a balun embedded driver stage to enhance the bandwidth and minimize the chip size of a differential CMOS power amplifier. By removing the passive input transformer, the bandwidth and chip size are improved. The proposed driver stage acts as an input balun as well as the driver stage for the power stage. The proposed driver is composed of a cascade connected PMOS, an inductor, and NMOS to generate the differential output signal. For the function of the input balun, the gate of the PMOS is connected to the drain of the NMOS. To verify the feasibility of the proposed balun embedded driver stage, we design a differential CMOS power amplifier for 5-GHz IEEE 802.11n WLAN applications. The designed power amplifier is fabricated using the 180-nm SOI RF CMOS process. The measured 3-dB bandwidth is approximately 2.5 GHz. The chip size of the fully integrated power amplifier, including input and output matching networks and test pads, is 0.885 mm 2. The measured maximum output power is 20.18 dBm with a PAE of 10.16%.

We propose a linear class‐D amplifier for the driver stages of RF CMOS linear power amplifiers. To minimize the chip areas for the driver stages of the linear power amplifiers, we propose a technique for the class‐D amplifier to be operated as a linear amplifier. The linear gain and proper bias point for the linear operation are obtained with additional load capacitance and a feedback resistor, respectively. To verify the feasibility of the proposed linear class‐D amplifier, we designed a 1.8‐GHz CMOS linear power amplifier with a differential structure using 180‐nm RF CMOS technology. From the measured linearity and maximum average output power with a WCDMA modulated input signal, we successfully verify the linear operation of the proposed linear class‐D amplifier. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:565–569, 2016