In this work, we design a linear CMOS power amplifier with a spiral‐type output transformer for IEEE 802.11n WLAN applications. We conduct studies to identify the proper output transformer and power stage structures for linear CMOS power amplifiers. The power amplifier is composed of a single differential‐pair for the power stage to mitigate the stability problems that frequently arise in high gain linear power amplifiers. Additionally, we investigate the output matching network using a spiral‐type output transformer to minimize the output return loss. To verify the feasibility of the power amplifier, we designed a 2.4‐GHz power amplifier with a 180‐nm SOI CMOS process. The designed power amplifier is measured using an IEEE 802.11n WLAN signal. The power amplifier achieves 21.28 dBm output power while the measured EVM satisfies the standard for 802.11n applications. © 2017 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:546–550, 2017

In this study, we propose a simple technique to enhance the efficiency of RF CMOS power amplifiers in which a cascode structure is utilized. To increase the efficiency in the low‐output‐power region, we split a common gate transistor into two parts. For the low‐output‐power mode, one of the common gate transistors is turned off to reduce the amount of DC power consumed. To verify the feasibility of the proposed split cascode structure, we designed a 2.2‐GHz CMOS power amplifier using the 180‐nm RF CMOS process. With a WCDMA modulated signal, we obtain a maximum‐output power of 23.4 dBm with 20.8% power‐added efficiency (PAE). At an output power of 16 dBm, the PAE is enhanced by the mode change of the designed power amplifier. From the measured results, we successfully verify the feasibility of the proposed split cascode structure for RF CMOS power amplifier applications. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:309–312, 2016

In this study, we propose a layout technique to reduce the chip area of differential RF CMOS power amplifiers in which input and output transformers are utilized as input and output baluns. To minimize the chip area of the CMOS power amplifier, we split a conventional spiral transformer into two identical parts, thereby making full use of the wasted area in the conventional power amplifier. Using the proposed split transformers in the input and output transformers, we successfully reduce the chip area of the CMOS power amplifier based on a differential structure. To verify the feasibility of the proposed split cascode structure, we designed a 2.4‐GHz CMOS power amplifier using a 180‐nm SOI RF CMOS process. With an IEEE 802.11n WLAN modulated signal, we obtain a maximum output power of 9.73 dBm. From the measured results, we verify the feasibility of the proposed split transformer structure for RF CMOS power amplifier applications. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:1443–1446, 2016

In this study, we design a differential CMOS power amplifier using a 180-nm SOI RFCMOS process for 802.11n (64-QAM, 20 MHz bandwidth, 9.6 dB peak to average power ratio (PAPR)) applications. To minimize the chip area and mismatch in differential signals, we propose a layout method with an inter-stage matching network using a split inductor. By virtue of the symmetrical layout of the proposed split inductor, the mismatch in the differential signals is minimized, while the interconnection lines between the driver and power stages are shortened to minimize the overall chip area and the loss induced by the resistive parasitic components. The designed power amplifier is measured using a wireless local area network (WLAN) 802.11n signal to verify the feasibility of the proposed layout technique. The power amplifier achieved 20.34 dBm output power, while the measured EVM for the 802.11n applications is satisfied. From the measured results, we successfully prove the feasibility of the proposed power amplifier.

In this paper, a 5.08 GHz Ring Voltage Controlled Oscillator(Ring VCO) was implemented using 0.18 μm standard CMOS technology. The proposal Ring VCO is 3-stage structure. This research confirmed that the each stage's different transistor size ratio influence the current change and alter power consumption consequentially. This circuit is formed to control the current thereby adding the Current Mirror and to tune the frequency by supplying control voltage. It has an 65.5 %(1.88～5.45 GHz) tuning range. The measured output power is -0.30 dBm. The phase noise is -87.50 dBc/Hz @1 MHz offset with operating frequency of 5.08 GHz fundamental frequency. The total power consumption of Ring VCO is 31.2 mW with 2.4 V supply voltage.