A linear CMOS power amplifier using class‐D to reduce the number of required inductors

Abstract

We propose a linear class‐D amplifier for the driver stages of RF CMOS linear power amplifiers. To minimize the chip areas for the driver stages of the linear power amplifiers, we propose a technique for the class‐D amplifier to be operated as a linear amplifier. The linear gain and proper bias point for the linear operation are obtained with additional load capacitance and a feedback resistor, respectively. To verify the feasibility of the proposed linear class‐D amplifier, we designed a 1.8‐GHz CMOS linear power amplifier with a differential structure using 180‐nm RF CMOS technology. From the measured linearity and maximum average output power with a WCDMA modulated input signal, we successfully verify the linear operation of the proposed linear class‐D amplifier. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:565–569, 2016

A Cmos Power Amplifier Using a Balun Embedded Driver Stage for Ieee 802.11N Wlan Applications

“…Given that a virtual AC ground can be easily obtained in the differential structure, the differential structure is very popular in the design of the CMOS power amplifiers; a schematic is provided in Fig. 1(b) [19,20]. Because of the virtual AC ground in the differential structure, the gain reduction problems induced by the bond-wires can be easily solved in CMOS power amplifiers.…”