Journal of Electronic Testing
 2000
DOI: 10.1023/a:1008302118244
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Hussain Al-Asaad1,
John P. Hayes2
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Cited by 7 publications
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References 25 publications
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Incremental Design Debugging in a Logic Synthesis Environment

Veneris
1
,
Liu2
2005
J Electron Test
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Incremental Design Debugging in a Logic Synthesis Environment

Veneris
1
,
Liu2
2005
J Electron Test
0
0
0
0
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Testing for Missing-Gate Faults in Reversible Circuits

Hayes
1
,
Polian
2
,
Becker
3
13th Asian Test Symposium
96
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64
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Advanced modeling of faults in Reversible circuits

Polian
1
,
Hayes
2
2010
2010 East-West Design &Amp; Test Symposium (EWDTS)
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