1.0-/spl mu/m n-Well CMOS/Bipolar Technology

Technology compatibility and circuit complementarity of BIMOS

“…The device performance of the BIMOS process outlined above is shown in Table 3. Among the BIMOS technologies reported from different groups, the work of Hitachi (Okada et al 1984(Okada et al , 1985 and Toshiba (Momose et al 1985) group seems to be the most mature. An advanced bipolar CMOS process is proposed by the Hitachi group which satisfactorily meets most of-the requirements of analogue and/or digital VLSI.…”

“…In the process outlined above IIL and MOS devices fabricated on the same chip have good performance. A high-performance 1.0pm n-well CMOS-bipolar technology for an analoguedigital combined VLSI chip was developed by Toshiba Corporation (Momose et al 1985). The n-well structure of CMOS has been chosen to realize collector isolated vertical n-pn bipolar transistors on the same chip.…”

“…Though the major work on BIMOS technology and integrated circuits (ICs) was confined to the RCA (USA.) group, Hitachi (Japan) (Okada et al 1984, Schade 1978, Toshiba (Japan) (Momose et al 1985), Universitat Dortmund (F.R. Germany) (Zimmer et al 1979), University of Waterloo & Toronto (Canada) (Eldin and Elmasry 1985, Krajewska and Holmes 1979, Hamdy and Elmasry 1980 and other groups (Waleszky andRubinstein 1983, Miyamoto el al.…”

“…Schematic cross-sections of the 1.0p-n n-well CMOS-bipolar structure of Toshiba without (upper) and with (lower) n+-buried layer (redrawn fromMomose et al 1985).…”