1.2–17.6 GHz Ring-Oscillator-Based Phase-Locked Loop with Injection Locking in 65 nm Complementary Metal Oxide Semiconductor

Lee, Sangyeop; Ito, Hiroyuki; Amakawa, Shuhei; Tanoi, Satoru; Ishihara, Noboru; Masu, Kazuya

doi:10.7567/jjap.51.02be03

Cited by 3 publications

(8 citation statements)

References 16 publications

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“…In this case, the charge-pump noise of the PLL is assumed to be sufficiently small and can be neglected. In this figure, the noise filtering of the loop has suppressed the phase noise up to the loop bandwidth (ω -3dB ) [3].…”

Section: (B) Figure 2(c)mentioning

confidence: 95%

“…Injection locking technique is an effective way for reducing the phase noise of oscillators specially ring types, since ring VCOs have a wide locking range with injection locking compared to LC VCOs because of their low quality factors due to topologies [3].…”

Section: (B) Figure 2(c)mentioning

confidence: 99%

“…where Q is the quality factor of the oscillator, ω out represents the output frequency of the oscillator under the injection locked condition, P inj,N is the N th harmonic power of the reference signal, and P 0 is the free-running output power of the oscillator [3]. Locking range determines the phase noise characteristics of the injection-locked PLL.…”

Section: (B) Figure 2(c)mentioning

confidence: 99%

“…In otherwise, if injection pulse width is too small, a small current flows through the switch and injection locking doesn't have enough energy for correcting the phase, even locking process may be failed. On the other hand, if width of injection pulse is larger than the rise/fall time of output signal of PLL, a large amount of current will be injected to the differential nodes and a large rotation in phase signal or a large spurious level may be occurred [3].…”

Section: Injection Signal Specificationsmentioning

confidence: 99%

“…However, if there is a method that can alleviate the poor phase noise problem, the ring VCOs can be introduced as a good option for many applications. One of these ways is using injection locking technique [3].…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

A Low Phase Noise Ring-VCO Based PLL Using Injection Locking for ZigBee Applications

Talebi¹,

Ghafoorifard

Sheikhaei³

et al. 2013

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A low power low phase noise frequency synthesizer with subharmonic injection locking is proposed for ZigBee applications. The PLL is based on a ring VCO to decrease area and production cost. In order to improve phase noise performance, a high frequency injection signal of which frequency varies with channel number is used. The circuit is designed in TSMC 0.18 μm CMOS technology and simulated in ADS (Advanced Design System). The phase noise at 3.5 and 10 MHz offsets is -116 and -118 dBc/Hz, respectively, and total circuit consumes 2.2 mA current

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Section: (B) Figure 2(c)mentioning

confidence: 95%

Section: (B) Figure 2(c)mentioning

confidence: 99%

Section: (B) Figure 2(c)mentioning

confidence: 99%

Section: Injection Signal Specificationsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A Low Phase Noise Ring-VCO Based PLL Using Injection Locking for ZigBee Applications

Talebi¹,

Ghafoorifard

Sheikhaei³

et al. 2013

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Low-noise sub-harmonic injection locked multiloop ring oscillator

Wei

et al. 2016

J. Semicond.

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A three-stage differential voltage-controlled ring oscillator is presented for wide-tuning and low-phase noise requirement of clock and data recovery circuit in ultra wideband (UWB) wireless body area network. To improve the performance of phase noise of delay cell with coarse and fine frequency tuning, injection locked technology together with pseudo differential architecture are adopted. In addition, a multiloop is employed for frequency boosting. Two RVCOs, the standard RVCO without the IL block and the proposed IL RVCO, were fabricated in SMIC 0.18 μm 1P6M Salicide CMOS process. The proposed IL RVCO exhibits a measured phase noise of −112.37 dBc/Hz at 1 MHz offset from the center frequency of 1 GHz, while dissipating a current of 8 mA excluding the buffer from a 1.8-V supply voltage. It shows a 16.07 dB phase noise improvement at 1 MHz offset compared to the standard topology.

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A fast-locking all-digital PLL with dynamic loop gain control and phase self-alignment mechanism for sub-GHz IoT applications

Yang

Wang

Chang

et al. 2020

Jpn. J. Appl. Phys.

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This paper describes a fast-locking all-digital phase-locked loop (ADPLL) with dynamic loop gain control and a phase self-alignment mechanism. Compared with conventional fast-locking ADPLLs, the ADPLL proposed in this paper features the phase self-alignment mechanism to resolve overdamping caused by a large KI. Therefore, the proposed ADPLL not only reduces locking time but also maintains jitter performance. In this paper, we used a 0.18 μm standard CMOS process with a supply voltage of 1.8 V. The experimental results indicated that the proposed ADPLL can reduce locking time by 91%. The output frequency range of the proposed ADPLL is 0.7–1 GHz, which is suitable for sub-GHz Internet of Things band applications. At 1 GHz, the power consumption was 10.93 mW, peak-to-peak jitter was 19.53 ps, locking time was 3.5 μs which is 35 TREF, and core area was 0.291 mm2.

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1.2–17.6 GHz Ring-Oscillator-Based Phase-Locked Loop with Injection Locking in 65 nm Complementary Metal Oxide Semiconductor

Cited by 3 publications

References 16 publications

A Low Phase Noise Ring-VCO Based PLL Using Injection Locking for ZigBee Applications

A Low Phase Noise Ring-VCO Based PLL Using Injection Locking for ZigBee Applications

Low-noise sub-harmonic injection locked multiloop ring oscillator

A fast-locking all-digital PLL with dynamic loop gain control and phase self-alignment mechanism for sub-GHz IoT applications

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