1.25 volt, low cost, embedded flash memory for low density applications

McPartland, Richard J.; Singh, Ritu

doi:10.1109/vlsic.2000.852878

Cited by 21 publications

(8 citation statements)

References 1 publication

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“…A dense modular SRAM cell with an area of 3.3 µm 2 is also available by tightening selected design rules and with the addition of one mask level for a self-aligned and borderless contact. Nonvolatile memory cells are also used to implement redundancy in dense memory arrays; this adds another modular process sequence and uses one additional mask level [4]. Buried fusible links are available when only a few bits are required, for example, when trimming voltage references or building in chip IDs.…”

Section: Dense Srammentioning

confidence: 99%

BiCMOS technology for mixed-digital, analog, and RF applications

Rich

Carroll²,

Frei³

et al. 2002

IEEE Microwave

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Section: Dense Srammentioning

confidence: 99%

BiCMOS technology for mixed-digital, analog, and RF applications

Rich

Carroll²,

Frei³

et al. 2002

IEEE Microwave

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“…However, using dedicated NV memories, such as embedded flash memory, is usually not cost-effective for those chips that require only a small NV capacity for, e.g., chip identification and trimming information storage, since the additional process cost necessary to fabricate the NV memory must be paid for the entire chip area, instead of only the small NV area. For such applications, an NV memory function on a CMOS chip that requires a minimal number of additional process steps [1][2][3][4][5][6][7][8][9][10] is desired. The use of one-time programmable (OTP) memories that do not require additional mask steps for their fabrication is a possible solution to meet such needs, even though the NV data can be programmed only once.…”

Section: Introductionmentioning

confidence: 99%

Parallel programmable nonvolatile memory using ordinary static random access memory cells

Mizutani

Takeuchi

Saraya

et al. 2017

Jpn. J. Appl. Phys.

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A technique of using an ordinary static random access memory (SRAM) array for a programmable nonvolatile (NV) memory is proposed. The parallel NV writing of the entire array is achieved by simply applying high-voltage stress to the power supply terminal, after storing inverted desired data in the static random access memory (SRAM) array. Successful 2 kbit NV writing is demonstrated using a device-matrix-array (DMA) test element group (TEG) fabricated by 0.18 µm technology.

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“…Because of the limitations of the compatibility between the resistive film deposition and Manuscript existing CMOS processes, it is hard to adapt the resistive film and its structure in CMOS circuits simply without impact to the CMOS logic process integration, performance, and yields [8], [9]. To satisfy the needs of low voltage operations, high scalability, and CMOS process adaptability, in this letter, a novel and simple two-transistor logic embedded RRAM cell with Taiwan Semiconductor Manufacturing Company (TSMC) 28-nm high-k metal gate (HKMG) fully CMOS compatible process has been first proposed and fabricated for realizing the low cost and low density logic NVM solution to meet the requirements of low density products such as analog trimming, memory redundancy and data encryption [10].…”

Section: Introductionmentioning

confidence: 99%

28-nm 2T High-<formula formulatype="inline"><tex Notation="TeX">$K$</tex></formula> Metal Gate Embedded RRAM With Fully Compatible CMOS Logic Processes

Mei

Shen

et al. 2013

IEEE Electron Device Lett.

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A new two-transistor embedded resistive RAM (RRAM) cell with fully Taiwan Semiconductor Manufacturing Company 28-nm CMOS logic compatible process is reported. The new 28-nm logic compatible RRAM cell consists of two logic standard high-k metal gate (HKMG) CMOS transistors with a composite resistive gate dielectric of TiN/HfO 2 /SiO 2 /Si as a resistive memory storage node. Using one of the transistor gates as a source line in RRAM SET/RESET operation, the resistive memory states can be efficiently read and sensed by selecting the other transistor gate and its corresponding bitline. Therefore, the new 2T embedded RRAM cell has realized a logic nonvolatile memory (NVM) solution with cost effective, and fully compatible with 28-nm HKMG CMOS logic platforms. Besides, through adapting the existing high-K gate dielectric in the RRAM cell, the embedded memory cell does not need any additional deposition of resistive film or extra process steps and it will be very scalable and compatible with the fast progress of CMOS technologies in embedded NVM applications. Furthermore, its low voltage requirement makes this cell conveniently fit in logic intellectual properties and circuits for local data storages or level trimming devices on system-on-chip logic NVM products.Index Terms-28-nm high-k metal gate (HKMG) CMOS logic process, embedded resistive RAM (RRAM), nonvolatile memory.

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1.25 volt, low cost, embedded flash memory for low density applications

Cited by 21 publications

References 1 publication

BiCMOS technology for mixed-digital, analog, and RF applications

BiCMOS technology for mixed-digital, analog, and RF applications

Parallel programmable nonvolatile memory using ordinary static random access memory cells

28-nm 2T High-<formula formulatype="inline"><tex Notation="TeX">$K$</tex></formula> Metal Gate Embedded RRAM With Fully Compatible CMOS Logic Processes

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