1.8 dB insertion loss 200 GHz CPW band pass filter integrated in HR SOI CMOS Technology

Gianesello, Frédéric; Gloria, D.; Montusclat, S.; Raynaud, C.; Boret, S.; Dambrine, G.; Lepilliet, S.; Martineau, Baudouin; Pilard, Romain

doi:10.1109/mwsym.2007.380486

Cited by 38 publications

(19 citation statements)

References 7 publications

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“…NF min and G ass vs frequency for 50x2x0.055 µm 2 n-MOSFET (VDS=0.7 V, IDS=100 mA/mm). (Gianesello, et al, 2007) we have focused our attention on coplanar transmission lines achieved on HR SOI. Since it has been demonstrated that in HR SOI substrate losses are drastically reduced, we propose here the use of a new stacked coplanar transmission line dedicated to HR SOI technology.…”

Section: Nm Mosfet Performancesmentioning

confidence: 99%

See 1 more Smart Citation

Trend on Silicon Technologies for Millimetre-Wave Applications up to 220 GHz

Prigent¹,

Vu²,

Rius³

et al. 2010

Microwave and Millimeter Wave Technologies From Photonic Bandgap Devices to Antenna and Applications

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Section: Nm Mosfet Performancesmentioning

confidence: 99%

“…26) which ensures a quasi-TEM propagation mode. State-of-the-art attenuation, in the order of 1 dB/mm @ 100GHz and 1.5 dB/mm @200 GHz, has been measured (Gianesello, Gloria et al, 2007). …”

Section: Nm Mosfet Performancesmentioning

confidence: 99%

Trend on Silicon Technologies for Millimetre-Wave Applications up to 220 GHz

Prigent¹,

Vu²,

Rius³

et al. 2010

Microwave and Millimeter Wave Technologies From Photonic Bandgap Devices to Antenna and Applications

View full text Add to dashboard Cite

“…4) which ensures a quasi-TEM propagation mode. State-of-the-art attenuation, in order of 1 dB/mm @ 100GHz and 1.5 dB/mm @200 GHz, has been measured [12]. IV.…”

Section: Nm Mosfet Performancesmentioning

confidence: 99%

65 nm HR SOI CMOS Technology: emergence of Millimeter-Wave SoC

Gianesello

Montusclat

Martineau

et al. 2007

2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium

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Today, measurement of 65 nm CMOS [1] and 130nm-based SiGe HBTs [2] technologies demonstrate both F T (current gain cut-off frequency) and Fmax (maximum oscillation frequency) higher than 200 GHz, which are clearly comparable to advanced commercially available 100 nm III-V HEMT. Consequently, the integration of full transceiver at 60 GHz has been achieved both in SiGe bipolar [3] and CMOS technology [4].In the same time passive circuits working @ 220 GHz have been achieved and characterized on High Resistivity SOI demonstrating state-of-the-art performances and good agreement with electrical simulations using developed models. Moreover, HR SOI has also demonstrated some advantages concerning the performances of integrated antennas [5] and a first fully integrated prototype with amplifier, filter and antenna has already been achieved using STMicroeletronics 130 nm CMOS HR SOI technology [6]. This paper will review the MMW performances of STMicrolectronics 65 nm CMOS HR SOI technology from device up to circuit level and discuss the opportunities of MMW SoC integrated on CMOS HR SOI technology.

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“…In the last decade, the advances in silicon technology have inspired an important trend towards the integration of RF devices on Si [1], [2]. Several solutions are investigated in this respect, the most important being the use of Si micromachining for the fabrication of free standing structures, used mainly in the fabrication of RF inductors [3], the use of high resistivity (HR) Si that is less lossy at RF than the low resistivity Si [4], the trap-rich HR-Si substrate [5], the HR-SOI substrate [6], or the trap-rich HR-SOI substrate [7] and porous Si (PSi) used as a local substrate on the low resistivity Si substrate [8], [9].…”

Section: Introductionmentioning

confidence: 99%

Porous Si dielectric parameter extraction for use in RF passive device integration: Measurements and simulations

Sarafis

Hourdakis

Nassiopoulou

2013

2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)

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The aim of this paper is to develop a formalism for porous Si dielectric parameter extraction for use in RF passive device design. We show that the extracted dielectric parameters using this formalism can be reliably used to simulate the experimental behavior of coplanar waveguides and inductors. In this respect we have fabricated RF devices on porous Si, extracted the dielectric parameters of the porous Si layer and used these parameters to simulate different RF devices, which are fabricated on the same type of material and tested experimentally. By comparing the simulations with the measurements a very good agreement is achieved.

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1.8 dB insertion loss 200 GHz CPW band pass filter integrated in HR SOI CMOS Technology

Cited by 38 publications

References 7 publications

Trend on Silicon Technologies for Millimetre-Wave Applications up to 220 GHz

Trend on Silicon Technologies for Millimetre-Wave Applications up to 220 GHz

65 nm HR SOI CMOS Technology: emergence of Millimeter-Wave SoC

Porous Si dielectric parameter extraction for use in RF passive device integration: Measurements and simulations

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