1∼99% Input Duty 50% Output Duty Cycle Corrector

Huang, Hong; Liang, Chia-Ming; Chiu, Wei-Ming

doi:10.1109/iscas.2006.1693549

Cited by 8 publications

(3 citation statements)

References 9 publications

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“…To ensure wide operation range, a single stage, rail-torail operational trans-conductance amplifier (OTA) proposed in [7] is adopted in the integrator, as shown in Fig. 4.…”

Section: Duty Cycle Detectormentioning

confidence: 99%

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1 MHz–3.5 GHz, wide range input duty 50% output duty cycle corrector

2011

Analog Integr Circ Sig Process

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A duty cycle corrector (DCC) is proposed in this paper. By directly controlling the duty cycle in the clock distribution path, it can work at a frequency as high as 3.5 GHz. The DCC adopts the continuous-time integrator as the duty cycle detector. The output pulse is scaled down according to the input frequency, which reduces the control voltage ripple and expands the minimum operation frequency to 1 MHz. The test chip is fabricated using SMIC 0.18 lm CMOS process. The experiment results show that the frequency range of the input signal was 1 MHz-3.5 GHz, and the duty cycle range of the input signal is from 0.1-99.9%. The peak-to-peak jitter and power dissipation are 33.3 ps and 0.6 mW, respectively, at an operating frequency of 2 GHz.

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“…To ensure wide operation range, a single stage, rail-torail operational trans-conductance amplifier (OTA) proposed in [7] is adopted in the integrator, as shown in Fig. 4.…”

Section: Duty Cycle Detectormentioning

confidence: 99%

“…The DCCs in existence can be generally categorized into Digital DCCs [1][2][3][4] and analog DCCs [5][6][7][8]. In general, digital DCCs are limited in the medium frequencies and of worse precision due to the unit delay cell.…”

Section: Introductionmentioning

confidence: 99%

1 MHz–3.5 GHz, wide range input duty 50% output duty cycle corrector

2011

Analog Integr Circ Sig Process

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“…The clock generation circuit generates clock signal, which is a fixed cycle and running independent signals, it is the base of a lot of circuit, and it can decide when the logic state updates. Most clock generation circuits are comprised of RS trigger, and the duty cycle of generated clock signal is equal 50% [6][7][8]. However, some circuits, such as charge pump circuit, when they use this signal, it will appear charge leakage and the mismatch of charging and discharging current [9][10][11].…”

Section: Introductionmentioning

confidence: 99%

A Design of High Frequency Clock Generation Circuit

Zhai

Gao

Tang

et al. 2013

AMM

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A clock generation circuit is proposed based on CMOSFET technology, which is comprised of a reference voltage source, a common source voltage amplifier, voltage controlled oscillator and timing circuit. By which a particular clock is produced, whose duty cycle is less than 50%. It is used 0.5 μ s CMOS process, HSPICE simulation results indicates that the average frequency of clock signal is 2.071MHz, and the average duty cycle is 31.565% .

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