1 GHz fully pipelined 3.7 ns address access time 8 k×1024 embedded DRAM macro

Takahashi, Osamu; Dhong, S.H.; Ohkubo, Masaru; Onishi, S.; Dennard, R.H.; Hannon, R.; Crowder, S.; Iyer, Subramanian S.; Wordeman, M.R.; Davari, B.; Weinberger, W.B.; Aoki, Naofumi

doi:10.1109/isscc.2000.839831

Cited by 6 publications

(6 citation statements)

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“…It seems likely that today's conventional DRAM will be embedded with microprocessors on the same chips and speeded up by utilizing the microprocessor devices and architectural improvements [87], while chips that perform only the memory function will continue to emphasize density, slower speed, and perhaps nonvolatility. Thus, DRAM may evolve in more than one direction in the future.…”

Section: A General Considerationsmentioning

confidence: 99%

Device scaling limits of Si MOSFETs and their application dependencies

et al. 2001

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This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metaloxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.

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Section: A General Considerationsmentioning

confidence: 99%

Device scaling limits of Si MOSFETs and their application dependencies

et al. 2001

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“…Throughput can be increased by employing high-speed memory (e.g., [17]) and high-speed I/O techniques (e.g., [18]) without the need to speed up the per-pixel ADCs, since their throughput scales linearly with array size. Fig.…”

Section: B Frame Ratementioning

confidence: 99%

A 10000 frames/s CMOS digital pixel sensor

Kleinfelder

Lim

Liu

et al. 2001

IEEE J. Solid-State Circuits

321

158

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Abstract-A 352 288 pixel CMOS image sensor chip with perpixel single-slope ADC and dynamic memory in a standard digital 0.18-m CMOS process is described. The chip performs "snapshot" image acquisition, parallel 8-bit A/D conversion, and digital readout at continuous rate of 10 000 frames/s or 1 Gpixels/s with power consumption of 50 mW. Each pixel consists of a photogate circuit, a three-stage comparator, and an 8-bit 3T dynamic memory comprising a total of 37 transistors in 9.4 9.4 m with a fill factor of 15%. The photogate quantum efficiency is 13.6%, and the sensor conversion gain is 13.1 V/e . At 1000 frames/s, measured integral nonlinearity is 0.22% over a 1-V range, rms temporal noise with digital CDS is 0.15%, and rms FPN with digital CDS is 0.027%. When operated at low frame rates, on-chip power management circuits permit complete powerdown between each frame conversion and readout. The digitized pixel data is read out over a 64-bit (8-pixel) wide bus operating at 167 MHz, i.e., over 1.33 GB/s. The chip is suitable for general high-speed imaging applications as well as for the implementation of several still and standard video rate applications that benefit from high-speed capture, such as dynamic range enhancement, motion estimation and compensation, and image stabilization.Index Terms-ADC, CMOS image sensor, digital pixel sensor, high-speed imaging, image sensor, memory.

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“…(Recently, a multiple oxide thickness and dual supply voltage device approach has become popular in e-DRAMs to achieve high performance and low leakage power (Takahashi et al 2000).) As with joint device sizing and supply and threshold voltage optimization, GP-based design can be carried out with multiple doping concentrations, channel lengths and oxide thicknesses, because models of gate delay as a function of doping concentration, channel length, and oxide thickness, as well as the device width, supply, and threshold voltage, can be well approximated as generalized posynomials.…”

Section: P -P|mentioning

confidence: 99%

Digital Circuit Optimization via Geometric Programming

Boyd

Kim

Patil

et al. 2005

Operations Research

154

146

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This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently solved. We start with a basic gate scaling problem, with delay modeled as a simple resistor-capacitor (RC) time constant, and then add various layers of complexity and modeling accuracy, such as accounting for differing signal fall and rise times, and the effects of signal transition times. We then consider more complex formulations such as robust design over corners, multimode design, statistical design, and problems in which threshold and power supply voltage are also variables to be chosen. Finally, we look at the detailed design of gates and interconnect wires, again using a formulation that is compatible with GP or GGP.

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1 GHz fully pipelined 3.7 ns address access time 8 k×1024 embedded DRAM macro

Cited by 6 publications

References 0 publications

Device scaling limits of Si MOSFETs and their application dependencies

Device scaling limits of Si MOSFETs and their application dependencies

A 10000 frames/s CMOS digital pixel sensor

Digital Circuit Optimization via Geometric Programming

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