10.1 A 116μ W 104.4dB-DR 100.6dB-SNDR CT Δ∑ Audio ADC Using Tri-Level Current-Steering DAC with Gate-Leakage Compensated Off-Transistor-Based Bias Noise Filter

Lo, Chi-Lun; Lee, Jongmi; Lim, Yong; Yoon, Younghyun; Hwang, Ho Jung; Lee, Jae‐Hoon; Choi, Min Suk; Lee, Myungjin; Oh, Sangyoon

doi:10.1109/isscc42613.2021.9365807

Cited by 7 publications

(3 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The ADCs in [1,9] have better FoM but are DT and require high-power input buffers to drive their switchedcapacitor front ends, resulting in overall higher system power. The ADCs in [6,7,8] have higher energy efficiency but are realized in more advanced technologies resulting in significantly lower digital power and area, especially for clock generation and the DWA logic. It should be noted that the designs in [6,7,8] Alias Rejection [dB]…”

Section: Measurement Resultsmentioning

confidence: 99%

See 1 more Smart Citation

A 590 µW, 106.6 dB SNDR, 24 kHz BW Continuous-Time Zoom ADC with a Noise-Shaping 4-bit SAR ADC

Mehrotra

Eland

Karmakar

et al. 2022

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)

View full text Add to dashboard Cite

This paper presents a continuous-time zoom ADC for audio applications. It combines a 4-bit noise-shaping coarse SAR ADC and a fine delta-sigma modulator with a tail-resistor linearized OTA for improved linearity, energy efficiency, and handling of out-of-band interferers compared to previous designs. In 160 nm CMOS, the prototype chip occupies 0.36 mm 2 , achieves 107.2 dB SNR, 106.6 dB SNDR, and 107.3 dB dynamic range in a 24 kHz bandwidth while consuming 590 µW from a 1.8 V supply. This translates into a Schreier figure-ofmerit (FoMS) of 183.4 dB and a FoMSNDR of 182.7 dB. Keywords-A/D conversion, audio analog to digital converter (ADC), continuous-time delta-sigma ADC, dynamic zoom ADC, low-power circuits, noise-shaping SAR ADC, high linearity operational transconductance amplifier (OTA)

show abstract

Section: Measurement Resultsmentioning

confidence: 99%

“…The ADCs in [6,7,8] have higher energy efficiency but are realized in more advanced technologies resulting in significantly lower digital power and area, especially for clock generation and the DWA logic. It should be noted that the designs in [6,7,8] Alias Rejection [dB]…”

Section: Measurement Resultsmentioning

confidence: 99%

A 590 µW, 106.6 dB SNDR, 24 kHz BW Continuous-Time Zoom ADC with a Noise-Shaping 4-bit SAR ADC

Mehrotra

Eland

Karmakar

et al. 2022

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)

View full text Add to dashboard Cite

show abstract

“…Three more energy-efficient audio ADCs are mentioned here, first, the work of Lee and Moon [117], where a DT single-loop ADC is implemented using ring-amplifier-based integrators in a mature 180-nm CMOS process. Lo et al [129] proposed a CT ADC, which offers easier drivability and an implicit anti-aliasing filter, in contrast to [117]. It uses a tri-level DAC like [128] but is based on a currentsteering DAC.…”

Section: ) Techniques For Narrowband Adcsmentioning

confidence: 99%

Design Techniques for Energy-Efficient Analog-to-Digital Converters

Jang,

Tang,

Lim

et al. 2023

IEEE Open J. Solid-State Circuits Soc.

Self Cite

View full text Add to dashboard Cite

The energy efficiency of analog-to-digital converters (ADCs) has improved steadily over the past 40 years, with the best reported ADC efficiency improving by nearly six orders of magnitude over the same period. The best figure-of-merit (FoM) is achieved with a limited class of ADC in terms of resolution and speed, but the coverage of the best FoM ADC has been expended. Many ADCs with the record FoM open up new applications and often incorporate multiple combinations of architectural and circuit innovations. It would be very interesting to follow a path of relentless optimization that could be useful to further expand the operating bandwidth of energy-efficient ADCs. To help along this path, this review article discusses the design techniques that focus on optimizing energy efficiency, involving successive approximation, pipelining, noise-shaping, and continuous-time operation.INDEX TERMS Analog-to-digital converter (ADC), continuous-time (CT), delta-sigma modulation, energy efficient, low power, noise-shaping (NS), pipelining, successive approximation.

show abstract