10–315-MHz Cascaded Hybrid Phase-Locked Loop for Pixel Clock Generation

Song, Minyoung; Kwak, Young-Ho; Ahn, Sung Tae; Park, Ho‐Jin; Kim, Chulwoo

doi:10.1109/tvlsi.2012.2227068

Cited by 2 publications

(2 citation statements)

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“…Therefore it suffers from poor jitter, large analog filter size and huge power consumptions if a normal integer-N PLL is used to realize the low jitter PCG. In [1], a digital loop filter is used to replace the large analog loop filter and [2] hires a cascaded PLL to reduce poor jitter. Others use an external crystal oscillator and a dual loop filter to mitigate performance degradation by jitter [3] [4] and the flying adder architecture also has been adopted [5].…”

Section: Introductionmentioning

confidence: 99%

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A 0.010mm<sup>2</sup> 9.92ps<inf>rms</inf> low tracking jitter pixel clock generator with a divider initializer and a nearest phase selector in 28nm CMOS technology

Choo

Kim

et al. 2014

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference

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A single loop low tracking jitter pixel clock generator is demonstrated in 28nm CMOS process. The proposed architecture only consists of a conventional single loop wide bandwidth fractional-N PLL and two synchronization skills which suppress the tracking jitter and bring out the delay control function like a DLL. When a 250MHz pixel clock is generated and synchronized with a 10kHz HSYNC, the measured tracking jitter is 9.92ps rms . The total power consumption is 9.7mW and the silicon area is only 0.010mm 2 in 28nm CMOS process.

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Section: Introductionmentioning

confidence: 99%

“…The measurement result shows that the short-term jitter of HSYNC is 103.2ps rms . Unfortunately, when the noisy HSYNC is applied to conventional narrow loop bandwidth PLL [1] [2][3] [4], its jitter is filtered out. The generated Pixel Clock becomes relatively cleaner and does not track the jitter of HSYNC anymore.…”

Section: Introductionmentioning

confidence: 99%