10-Gb/s limiting amplifier and laser/modulator driver in 0.18-μm CMOS technology

Wide modulation bandwidth terahertz detection in 130 nm CMOS technology

“…With this high source resistance, the input capacitance of the first stage needs to be as low as ∼25 fF to obtain a 15 GHz overall bandwidth. To achieve that, a combination of f t doubler, active feedback, and shunt peaking has been employed in the first stage [33,34]. In the f t doubler circuit, the input signal is fed to a series combination of two FETs, thus halving the input capacitance.…”

A 4-Channel Multi-Rate VCSEL Driver with Automatic Power, Magnitude Calibration using High-Speed Time-Interleaved Flash-SAR ADC in 0.13 ㎛ CMOS

“…Also, this is applied to M 10 and M 11 [4]. Using inductors L 1 and L 2, the overall bandwidth of the VCSEL driver core can be increased by the peaking in the magnitude response around the signal bandwidth [3,11].…”

“…The automatic power and magnitude calibration are implemented for the constant output power. External monitoring photo diodes (MPDs) are adopted to monitor the output power of the VCSEL diode in the conventional automatic power and magnitude calibration, which increases the system cost and area [4,5].…”

A multi-channel current-mode CMOS optical receiver array for active optical HDMI cables

“…Fig. 4 illustrates the block diagram of the gain-scaling limiting amplifier (LA) which comprises five-stage amplifiers, an offset cancellation circuit, and an output buffer [7,10]. The first two gain-cells take the configuration of Cherry-Hooper differential pair to mitigate the loading effect of the CM-TIA, whereas the next three gain-cells exploit source-degeneration technique so that the bandwidth maintains for 2.5-Gb/s operation speed per channel.…”