10 Gb/s very short reach transmission in parallel optical link

Wang, Zhigong

doi:10.1007/s00202-007-0063-5

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Fig2 Input Stage Circuit1

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2013

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“…In result, equation (7) shows that the circuit of second order active degenerative feedback system can improve the GBW (gain-bandwidth) to The last part is output circuit made up of C 3 A (capacitive coupled current amplifier) structure under 3.3V supply. This structure can decrease the falling time of output voltage, making the output voltage falling edge steeper.…”

Section: Fig2 Input Stage Circuitmentioning

confidence: 99%

Design of 10Gb/s VCSEL Driver IC in 0.18μm CMOS

Li¹,

Zhao²

2013

AMR

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A design of 10Gb/s VCSEL driver IC in 0.18μm CMOS process is presented. Employing directly coupled three stages of differential amplifiers, active degenerative feedback and C3A structure, the monolithically integrated circuit can amplify the amplitude of input differential signal to 22mA and offer a bandwidth of 9.4GHz at 10Gb/s with a total power consumption of about 91mW. The driver circuit can offer adjustable modulation current from 1 to 16mA and adjustable bias current from 1 to 10mA. The VCSEL driver can be used in the STM-64 optical fiber communication system.

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Section: Fig2 Input Stage Circuitmentioning

confidence: 99%