100-V Class Two-step-oxide Field-Plate Trench MOSFET to Achieve Optimum RESURF Effect and Ultralow On-resistance

Kobayashi, K.; Kato, Hiroaki; Nishiguchi, Toshifumi; Shimomura, S.; Ohno, Tetsuya; Nishiwaki, Tatsuya; Aida, Kikuo; Ichinoseki, Kentaro; Oasa, Kohei; Kawaguchi, Yusuke

doi:10.1109/ispsd.2019.8757615

Cited by 21 publications

(11 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Therefore, a higher resistivity bottom EPI spec is required to sustain a high rating voltage that results in a higher R on than the triple-EPIs design. Compared with other methods mentioned in [15,[18][19][20][21], the multiple-EPIs structure does not complicate the process in manufacturing, and a higher-V BR and a lower-R on,sp device can be achieved. We also use the same method to construct 200 V SGT devices with different EPI designs.…”

Section: Resultsmentioning

confidence: 99%

“…When the device rating voltage reaches 150-200 V, the drift resistance occupies about 90% of the total device resistance [16,18]. To achieve a high breakdown voltage (V BR ) design without increasing the R on too much, a gradient, two-stepped oxide or multiple stepped oxide designs were applied to the trenches and shown to improve device performance effectively [18][19][20][21]. Since the potential of the field plate (bottom gate) on the oxide around it is different everywhere, that leads to a different depletion strength and electric field between two trenches along the cell depth, [18][19][20][21] use oxide engineering to improve device performance.…”

Section: Introductionmentioning

confidence: 99%

“…To achieve a high breakdown voltage (V BR ) design without increasing the R on too much, a gradient, two-stepped oxide or multiple stepped oxide designs were applied to the trenches and shown to improve device performance effectively [18][19][20][21]. Since the potential of the field plate (bottom gate) on the oxide around it is different everywhere, that leads to a different depletion strength and electric field between two trenches along the cell depth, [18][19][20][21] use oxide engineering to improve device performance. On the other hand, double split-gate resurf stepped oxide UMOS can overcome the non-uniform problem [15]; however, the oxide and poly process in the trenches is too complicated.…”

Section: Introductionmentioning

confidence: 99%

“…This unique merit allows for the possibility of the double-EPIs design to reduce R on,sp , as well as its power consumption. In this study, we wanted to design and modify the EPI structures rather than the complicated fabrication ways mentioned in [15,[18][19][20][21], to reduce device R on and sustain a high V BR at the same time. When device ranting voltage is designed to over 100 V, we find that the R on of double-EPIs structure is no longer satisfying our expectations.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

150–200 V Split-Gate Trench Power MOSFETs with Multiple Epitaxial Layers

et al. 2020

View full text Add to dashboard Cite

A rating voltage of 150 and 200 V split-gate trench (SGT) power metal-oxide- semiconductor field-effect transistor (Power MOSFET) with different epitaxial layers was proposed and studied. In order to reduce the specific on-resistance (Ron,sp) of a 150 and 200 V SGT power MOSFET, we used a multiple epitaxies (EPIs) structure to design it and compared other single-EPI and double-EPIs devices based on the same fabrication process. We found that the bottom epitaxial (EPI) layer of a double-EPIs structure can be designed to support the breakdown voltage, and the top one can be adjusted to reduce the Ron,sp. Therefore, the double-EPIs device has more flexibility to achieve a lower Ron,sp than the single-EPI one. When the required voltage is over 100 V, the on-state resistance (Ron) of double-EPIs device is no longer satisfying our expectations. A triple-EPIs structure was designed and studied, to reduce its Ron, without sacrificing the breakdown voltage. We used an Integrated System Engineering-Technology Computer-Aided Design (ISE-TCAD) simulator to investigate and study the 150 V SGT power MOSFETs with different EPI structures, by modulating the thickness and resistivity of each EPI layer. The simulated Ron,sp of a 150 V triple-EPIs device is only 62% and 18.3% of that for the double-EPIs and single-EPI structure, respectively.

show abstract

Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

150–200 V Split-Gate Trench Power MOSFETs with Multiple Epitaxial Layers

et al. 2020

View full text Add to dashboard Cite

show abstract

“…It is based on utilizing an electrode embedded within an oxide-coated deep trench as a part of the drift region [5]. Subsequently, a split-gate RSO (SGRSO) UMOSFET [11][12][13][14][15][16][17][18][19][20] with an isolated field-plate (FP) between the gate and drain has been proposed. Compared with the RSO UMOSFET and typical trench MOSFET, it exhibits relatively low switching losses.…”

Section: Introductionmentioning

confidence: 99%

Simulation and Result Analysis of Split Gate Resurf Stepped Oxide UMOFSET with Floating Electrode for Improved Performance

et al. 2019

View full text Add to dashboard Cite

In this study, a split-gate resurf stepped oxide with a floating electrode (FSGRSO) UMOSFET has been proposed. The source in the trench is divided into two electrodes, namely: the upper electrode and the lower electrode. The upper one is the floating electrode, which redistributes the electric potential vertically, and improves the breakdown voltage and figure of merit (FOM). The breakdown (BV) and FOM of the FSGRSO UMOSFET have been improved up to 27.3% and 62.7%, respectively, compared with the SGRSO UMOSFET, according to the simulation results.

show abstract

A Model of Wafer Warpage for Trench Field‐Plate Power MOSFETs

Kato,

Cai,

Yuan

et al. 2024

Physica Status Solidi (a)

View full text Add to dashboard Cite

A new wafer warpage model is proposed for the full process design of trench field‐plate (FP) power metal‐oxide‐semiconductor fileld‐effect transitors (MOSFETs) using large‐sized wafer. Trench FP power MOSFETs feature a deep trench and thick oxide at the wafer surface. Wafer warpage occurs due to the stress imbalance between the front and back sides of the wafer. This warpage leads to significant problems with transport errors in manufacturing equipment. This issue is expected to become even more crucial as lateral pitch narrowing is employed to reduce on‐resistance. In this study, two methods are compared to estimate the warpage of a 200 mm diameter Si‐wafer after trench etching and oxidation process. The mechanical stress generated by the oxidation process in several cell units is calculated using a 3D simulation. In the first approach, wafer warpage is converted from the displacement of the cell units. In the second approach, wafer warpage is estimated based on the surface film stress, which is calculated in the 3D simulation. The second approach shows good agreement with experimental results and is applicable to the 300 mm diameter Si process. This method yields more accurate measurements than the method using displacement.

show abstract

100-V Class Two-step-oxide Field-Plate Trench MOSFET to Achieve Optimum RESURF Effect and Ultralow On-resistance

Cited by 21 publications

References 10 publications

150–200 V Split-Gate Trench Power MOSFETs with Multiple Epitaxial Layers

150–200 V Split-Gate Trench Power MOSFETs with Multiple Epitaxial Layers

Simulation and Result Analysis of Split Gate Resurf Stepped Oxide UMOFSET with Floating Electrode for Improved Performance

A Model of Wafer Warpage for Trench Field‐Plate Power MOSFETs

Contact Info

Product

Resources

About