100MHz-to–1GHz open-loop ADDLL with fast lock-time for mobile applications

Abstract

This paper presents a fast-lock wide-range all-digital delay locked loops (ADDLL) for mobile applications. The proposed open-loop architecture based on time-to-digital converter (TDC) has a lock time of 3~10 clock cycles. The multipath delay line is implemented to achieve high resolution in TDC. The frequency range selector is adopted for a wide-range operation. The ADDLL is implemented in a 0.18ȝm CMOS process and operates from 100MHz to 1GHz.