A fast-locking digital DLL with a high resolution time-to-digital converter

Zhang, Dandan; Yang, Haigang; Chen, Zhujia; Li, Wei; Huang, Zhihong; Lijiang, Gao; Zhu, Wei

doi:10.1109/cicc.2013.6658530

Cited by 11 publications

(3 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The proposed DLL-based CDR meets the short locking time and wide capture range requirement by utilizing TDC and DCDL [6] to coarsely lock the CDR. Besides, the proposed structure prevents the possibility of false locking.…”

Section: A Tdc and Dcdlmentioning

confidence: 99%

180.5Mbps-8Gbps DLL-based clock and data recovery circuit with low jitter performance

Liu

Wang

Jia

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

A wide range delay-locked loop (DLL) based clock and data recovery (CDR) circuit including coarse and fine tune blocks is proposed in this paper. The coarse tune block adopts a time to digital converter and digital control delay line to widen the frequency capture range, reduce locking time and prevent the false locking problem. In the fine tune block, a novel phase detector combines the tasks of sampling and charge-pump using half rate clock. Starting-control circuit can ensure CDR takes full use of the delay range provided by voltage control delay line. Moreover, a fully analog DLL technique is applied to exploit the benefits of low skew and jitter performance. The simulation result shows the proposed CDR can cover a wide frequency range from 180.5Mbps to 8Gbps, while the peak-to-peak jitter of recovery clock is 2.7ps at 200Mbps and 1.06ps at 8Gbps. Fabricated in a 65nm CMOS process, this design dissipates 9.9mW and 22.9mW respectively at 200 Mbps and 8Gbps from a 1.2 V supply. Keywords-Clock and data recovery (CDR), wide-range, delaylocked loop (DLL), low jitter, time-to-digital converter (TDC)

show abstract

Section: A Tdc and Dcdlmentioning

confidence: 99%

180.5Mbps-8Gbps DLL-based clock and data recovery circuit with low jitter performance

Liu

Wang

Jia

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

show abstract

“…Every cycle, input pulses T IN > 0 and T IN < 0 are amplified by TA and the amplified pulses are converted into code A1 and code A2 by TDC. Similarly, a maximum load compensation loop is performed 2 10 − 1 = 1023 cycles with input pulses T IN > 0 for TA gains 2x and 16x, and there are 8 loops in load calibration. In addition, as most of the runtime of TDC overlaps with the runtime of TA, we need only consider the TA runtime and the data comparison time in each cycle.…”

Section: ) Calibration Timementioning

confidence: 99%

All-Digital Mismatched Calibrator and Compensator for SR Latch-Based Variable-Gain Time Amplifier

Chao¹,

Lai²,

Hsu³

2020

IEEE Access

View full text Add to dashboard Cite

Two major mismatches in SR latch-based time amplifiers (TA) include input skew, which causes gain imbalance, and loading mismatch, which reduces gain accuracy. Accordingly, we propose an all-digital mismatched self-calibrator and compensator for an SR latch-based variable-gain TA. Tunable matching cells and variable capacitors are built into TAs to compensate for input skew (gain imbalance) and loading mismatch (gain inaccuracy). To ensure that the proposed calibration works efficiently and accurately, the TA must provide at least high and low gains where the low gain calibrates the most significant bit (MSB) and the high gain calibrates the least significant bit (LSB). This self-calibrator costs 4375 gates, and the power consumption is 2.8 mA for the TA gain with 2 and 3.2 mA for the TA gain with 16 at a sampling rate of 10 MHz. INDEX TERMS Mismatch calibration, self-calibration, time amplifier.

show abstract

“…However the is limited by the structure of PD and associated with the counts of clock cycles to complete synchronization. In this paper, we choose as in Equation (16). And the parameter satisfies the constraint T R =8 < < T R =7.…”

Section: Circuits Of the DCCmentioning

confidence: 99%

A high-precision synchronization circuit for clock distribution

et al. 2015

View full text Add to dashboard Cite

In this paper, a novel structure of a high-precision synchronization circuit, HPSC, using interleaved delay units and a dynamic compensation circuit is proposed. HPSCs are designed for synchronization of clock distribution networks in large-scale integrated circuits, where high-quality clocks are required. The application of a hybrid structure of a coarse delay line and dynamic compensation circuit performs roughly the alignment of the clock signal in two clock cycles, and finishes the fine tuning in the next three clock cycles with the phase error suppressed under 3.8 ps. The proposed circuit is implemented and fabricated using a SMIC 0.13 m 1P6M process with a supply voltage at 1.2 V. The allowed operation frequency ranges from 200 to 800 MHz, and the duty cycle ranges between OE20%; 80%. The active area of the core circuits is 245 134 m 2 , and the power consumption is 1.64 mW at 500 MHz.

show abstract

A fast-locking digital DLL with a high resolution time-to-digital converter

Cited by 11 publications

References 10 publications

180.5Mbps-8Gbps DLL-based clock and data recovery circuit with low jitter performance

180.5Mbps-8Gbps DLL-based clock and data recovery circuit with low jitter performance

All-Digital Mismatched Calibrator and Compensator for SR Latch-Based Variable-Gain Time Amplifier

A high-precision synchronization circuit for clock distribution

Contact Info

Product

Resources

About