10nm high performance mobile SoC design and technology co-developed for performance, power, and area scaling

Yang, Shu Ching; Liu, Yanxiang; Cai, Ming; Bao, Jerry; Feng, Peijie; Chen, Xiangdong; Ge, Lixin; Yuan, Jun; Choi, Jihong; Liu, Ping; Suh, You‐Seok; Wang, Hao; Deng, Jie; Gao, Yandong; Yang, Yang; Wang, Xiaoyong; Yang, Dongyun; Zhu, John; Penzes, Paul; Song, Seung Chul; Park, Chulyong; Kim, Sung-Won; Kim, Jedon; Kang, Shih-Chung; Terzioglu, E.; Rim, K.; Chidambaram, P.R.

doi:10.23919/vlsit.2017.7998203

Cited by 13 publications

(2 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The transceiver achieved the bandwidth density of 180 Gb/s/mm 2 with 10% of the effective area occupied by photonics, which can be reduced to 5% by optimizing the floorplan. Incorporating this photonics platform in advanced sub-10 nm technology nodes with higher transistor densities 33 This caused dielectric residues on the wafer after photonic trench planarization. We also experienced metal residues after the fabrication of the first via contact.…”

mentioning

confidence: 99%

Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip

Atabaki

Moazeni

Pavanello

et al. 2018

Nature

738

403

View full text Add to dashboard Cite

show abstract

mentioning

confidence: 99%

Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip

Atabaki

Moazeni

Pavanello

et al. 2018

Nature

738

403

View full text Add to dashboard Cite

show abstract

“…Si fin-shaped field-effect transistors (FinFETs) have been scaled down to 10-nm node through higher aspect ratio and layout optimization [1]. FinFETs started to substitute planar MOSFETs through design-technology co-optimization in terms of performance, power, and area for system-on-chip applications [2]. However, there are several technical concerns to be considered for further scaling.…”

Section: Introductionmentioning

confidence: 99%

Device Design Guideline of 5-nm-Node FinFETs and Nanosheet FETs for Analog/RF Applications

Yoon

Baek

2020

IEEE Access

View full text Add to dashboard Cite

Analog/RF performances of 5-nm node bulk fin-shaped field-effect transistors (FinFETs) and nanosheet FETs (NSFETs) were investigated and compared thoroughly using fully-calibrated TCAD. NSFETs have greater current drivability and gate-to-channel controllability than FinFETs under the same footprint, thus achieving larger intrinsic gain. But the cutoff frequencies (F t) of FinFETs and NSFETs are comparable due to larger gate capacitances (C gg) of NSFETs compensating DC performance improvements. Gate resistances (R g) of NSFETs are larger because of their metal gate (MG) configuration surrounding the channels, longer MG height by the topmost NS spacing region, and the bottom transistor, thus degrading maximum oscillation frequency (F max). Device design guidelines of FinFETs and NSFETs are also studied for better intrinsic gain, F t , and F max. Intrinsic gain is improved by better electrostatics, whereas F t increases by greater current drivability over C gg. For larger F max , careful device design is required to compensate between R g , C gg , output resistance, and F t. Overall, NSFETs outperform FinFETs in terms of intrinsic gain, F t , and F max , thus NSFETs are promising for analog/RF applications.

show abstract

Analog/Mixed-Signal Design in FinFET Technologies

Loke

Terzioglu

Kumar

et al. 2017

Hybrid ADCs, Smart Sensors for the IoT, and Sub-1v &Amp; Advanced Node Analog Circuit Design

View full text Add to dashboard Cite

10nm high performance mobile SoC design and technology co-developed for performance, power, and area scaling

Cited by 13 publications

References 0 publications

Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip

Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip

Device Design Guideline of 5-nm-Node FinFETs and Nanosheet FETs for Analog/RF Applications

Analog/Mixed-Signal Design in FinFET Technologies

Contact Info

Product

Resources

About