Device Design Guideline of 5-nm-Node FinFETs and Nanosheet FETs for Analog/RF Applications

Abstract

Analog/RF performances of 5-nm node bulk fin-shaped field-effect transistors (FinFETs) and nanosheet FETs (NSFETs) were investigated and compared thoroughly using fully-calibrated TCAD. NSFETs have greater current drivability and gate-to-channel controllability than FinFETs under the same footprint, thus achieving larger intrinsic gain. But the cutoff frequencies (F t) of FinFETs and NSFETs are comparable due to larger gate capacitances (C gg) of NSFETs compensating DC performance improvements. Gate resistances (R g) of NSFETs are larger because of their metal gate (MG) configuration surrounding the channels, longer MG height by the topmost NS spacing region, and the bottom transistor, thus degrading maximum oscillation frequency (F max). Device design guidelines of FinFETs and NSFETs are also studied for better intrinsic gain, F t , and F max. Intrinsic gain is improved by better electrostatics, whereas F t increases by greater current drivability over C gg. For larger F max , careful device design is required to compensate between R g , C gg , output resistance, and F t. Overall, NSFETs outperform FinFETs in terms of intrinsic gain, F t , and F max , thus NSFETs are promising for analog/RF applications.

Inner Spacer Engineering to Improve Mechanical Stability in Channel-Release Process of Nanosheet FETs

“…It was found that mechanical deformation could be reduced when TNS is thick, because of increased D. In the case of an n-type NS FET, a few nanometers of inner spacer is deposited between the nanosheets. Currently, most reports related with inner spacer have been performed in terms of electrical performance [20][21][22][23][24]. However, in view of the mechanical stress, the inner spacer plays a large role in the support of each nanosheet.…”

Digital/Analog Performance Optimization of Vertical Nanowire FETs Using Machine Learning

“…where Cgg is gate capacitance, Vdd is operation voltage fixed to 0.7 V, Ion is on-state current, Ft is cut-off frequency, and Gm is transconductance. Here Ft is simply calculated as Gm/(2πCgg), which is valid to non-planar devices [20]. RC delay and RF FoM are logged and then standardized to improve the ML training as in [15].…”

Device Design Guidelines of 3-nm Node Complementary FET (CFET) in Perspective of Electrothermal Characteristics

“…Conventional FinFETs, which have recently been scaled down to 5-nm nodes, have almost reached physical limits in reducing fin thickness [1]. Thus, to improve gate controllability, nanosheet FETs (NSHFETs) with gate-allaround (GAA) structures have been actively developed for sub-3-nm nodes [1]- [3]. However, they will continue to face these down-scaling limitations in the future.…”